中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

74 records (took 0.025 seconds)

    Methods of forming memory cells; and methods of forming vertical structures
    22.
    发明授权
    Methods of forming memory cells; and methods of forming vertical structures 有权
    形成记忆细胞的方法 以及形成垂直结构的方法

    公开(公告)号：US09059115B2

    公开(公告)日：2015-06-16

    申请号：US14097003

    申请日：2013-12-04

    Applicant: Micron Technology, Inc.

    Inventor： David A. Kewley ,  Brian Cleereman ,  Stephen W. Russell ,  Rex Stone ,  Anthony C. Krauth

    IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/28 ,  H01L27/115

    CPC classification number: H01L21/32133 ,  H01L21/0337 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/32139 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

    Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

    Abstract translation: 一些实施例包括形成存储器的方法。 可以在栅极堆叠上形成一系列光致抗蚀剂特征，并且可以在所述串联的末端形成占位符。 占位符可以通过间隙与所述系列的端部间隔开。 可以在光致抗蚀剂特征之上和之间在占位符上方以及在所述间隙内形成层。 该层可以沿光致抗蚀剂特征的边缘各向异性地蚀刻成多个第一垂直结构，并且沿着占位符的边缘进入第二垂直结构。 可以在第二垂直结构上形成掩模。 随后，可以使用第一垂直结构来模拟串门，同时使用掩模来对选择门进行图案化。 一些实施例包括形成导电流道的方法，并且一些实施例可以包括半导体结构。

    WORD LINE STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS
    23.
    发明公开
    WORD LINE STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS 审中-公开

    公开(公告)号：US20240029772A1

    公开(公告)日：2024-01-25

    申请号：US18377279

    申请日：2023-10-05

    Applicant: Micron Technology, Inc.

    Inventor： Stephen W. Russell ,  Lorenzo Fratin ,  Enrico Varesi ,  Paolo Fantini

    IPC: G11C8/10 ,  G11C8/14 ,  H01L23/522 ,  H10B63/00 ,  H10N70/00

    CPC classification number: G11C8/10 ,  G11C8/14 ,  H01L23/5226 ,  H10B63/84 ,  H10N70/021 ,  H10N70/826

    Abstract: Methods, systems, and devices for word line structures for three-dimensional memory arrays are described. A memory device may include word line structures that support accessing memory cells arranged in a three-dimensional level architecture. The word line structures may be arranged above a substrate and be separated from each other by respective dielectric layers. Each word line structure may include word line members and a word line plate that is connected to each word line member. Each word line plate may include a contact that may be coupled with a word line decoder operable to bias the word line plate. To couple the word line plate to the word line decoder, the memory device may include first vias that extend through holes in the word line plates and are coupled with second vias that extend from a respective contact through openings in the word line plates above the contact.

    TRENCH AND PIER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS
    24.
    发明公开
    TRENCH AND PIER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS 审中-公开

    公开(公告)号：US20230329010A1

    公开(公告)日：2023-10-12

    申请号：US17714771

    申请日：2022-04-06

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Russell L. Meyer ,  Stephen W. Russell ,  Lorenzo Fratin

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  H01L45/06 ,  H01L45/141 ,  H01L45/1675

    Abstract: Methods, systems, and devices for trench and pier architectures for three-dimensional memory arrays are described. A semiconductor device (e.g., a memory die) may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide support for subsequent processing. For example, a memory die may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. Pier structures may be formed in contact with the cross sectional patterns such that, when either the first material or the second material is removed to form voids, the pier structures may provide mechanical support of the cross-sectional pattern of the remaining material. In some examples, such pier structures may be formed within or along trenches or other features aligned along a direction of a memory array, which may provide a degree of self-alignment for subsequent operations.

    WORD LINE STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS
    25.
    发明公开
    WORD LINE STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS 审中-公开

    公开(公告)号：US20230307025A1

    公开(公告)日：2023-09-28

    申请号：US17656283

    申请日：2022-03-24

    Applicant: Micron Technology, Inc.

    Inventor： Stephen W. Russell ,  Lorenzo Fratin ,  Enrico Varesi ,  Paolo Fantini

    IPC: G11C8/10 ,  G11C8/14 ,  H01L23/522 ,  H01L27/24 ,  H01L45/00

    CPC classification number: G11C8/10 ,  G11C8/14 ,  H01L23/5226 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1608

    Abstract: Methods, systems, and devices for word line structures for three-dimensional memory arrays are described. A memory device may include word line structures that support accessing memory cells arranged in a three-dimensional level architecture. The word line structures may be arranged above a substrate and be separated from each other by respective dielectric layers. Each word line structure may include word line members and a word line plate that is connected to each word line member. Each word line plate may include a contact that may be coupled with a word line decoder operable to bias the word line plate. To couple the word line plate to the word line decoder, the memory device may include first vias that extend through holes in the word line plates and are coupled with second vias that extend from a respective contact through openings in the word line plates above the contact.

    Microelectronic devices with self-aligned interconnects, and related methods
    26.
    发明授权
    Microelectronic devices with self-aligned interconnects, and related methods 有权

    公开(公告)号：US11764146B2

    公开(公告)日：2023-09-19

    申请号：US17379257

    申请日：2021-07-19

    Applicant: Micron Technology, Inc.

    Inventor： Stephen W. Russell ,  Fabio Pellizzer ,  Lorenzo Fratin

    IPC: H01L21/00 ,  H01L23/522 ,  H01L21/768

    CPC classification number: H01L23/5226 ,  H01L21/76846 ,  H01L21/76871 ,  H01L21/76877

    Abstract: Methods for forming microelectronic device structures include forming interconnects that are self-aligned with both a lower conductive structure and an upper conductive structure. At least one lateral dimension of an interconnect is defined upon subtractively patterning the lower conductive structure along with a first sacrificial material. At least one other lateral dimension of the interconnect is defined by patterning a second sacrificial material or by an opening formed in a dielectric material through which the interconnect will extend. A portion of the first sacrificial material, exposed within the opening through the dielectric material, along with the second sacrificial material are removed and replaced with conductive material(s) to integrally form the interconnect and the upper conductive structure. The interconnect occupies a volume between vertically overlapping areas of the lower conductive structure and the upper conductive structure, where such overlapping areas coincide with the opening through the dielectric material.

    TECHNIQUES FOR FORMING SELF-ALIGNED MEMORY STRUCTURES
    29.
    发明申请
    TECHNIQUES FOR FORMING SELF-ALIGNED MEMORY STRUCTURES 有权

    公开(公告)号：US20230027799A1

    公开(公告)日：2023-01-26

    申请号：US17881274

    申请日：2022-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Stephen W. Russell ,  Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Lorenzo Fratin

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

Patent Agency Ranking