公开(公告)号：US20220246736A1

公开(公告)日：2022-08-04

申请号：US17167853

申请日：2021-02-04

Applicant: Micron Technology, Inc.

Inventor： Sandeep Ramasamudra Suresha ,  Terrence B. McDaniel

IPC: H01L29/417 ,  H01L29/45 ,  H01L21/283 ,  H01L29/40 ,  H01L27/108 ,  H01L29/78

Abstract: A microelectronic device comprises a conductive structure, a metal nitride material, and a metal silicide material. The conductive structure comprises a first portion having a first width, and a second portion under the first portion and extending into a semiconductive material. The second portion has a tapered profile defining additional widths varying from the first width at an upper boundary of the second portion to a second width less than the first width at a lower boundary of the second portion. The metal nitride material substantially surrounds outer surfaces of the first portion and the second portion of the conductive structure. The metal silicide material substantially covers outer surfaces of the metal nitride material within vertical boundaries of the second portion of the conductive structure. Related methods, memory devices, and electronic systems are also described.

公开(公告)号：US11257766B1

公开(公告)日：2022-02-22

申请号：US16999817

申请日：2020-08-21

Applicant: Micron Technology, Inc.

Inventor： Russell A. Benson ,  Davide Colombo ,  Yan Li ,  Terrence B. McDaniel ,  Vinay Nair ,  Silvia Borsari

IPC: H01L23/552 ,  H01L27/108

Abstract: A method of forming a microelectronic device comprises forming a conductive shielding material over a conductive shielding structure and a first dielectric structure horizontally adjacent the conductive shielding structure. A second dielectric structure is formed on first dielectric structure and horizontally adjacent the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending in parallel in a first horizontal direction. Each of the fin structures comprises two dielectric end structures integral with remaining portions of the second dielectric structure, and an additional conductive shielding structure interposed between the two dielectric end structures in the first horizontal direction. Conductive lines are formed to extend in parallel in the first horizontal direction and to horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20240292603A1

公开(公告)日：2024-08-29

申请号：US18505462

申请日：2023-11-09

Applicant: Micron Technology, Inc.

Inventor： Russell A. Benson ,  Terrence B. McDaniel ,  Vinay Nair

IPC: H10B12/00 ,  H01L21/762

CPC classification number: H10B12/482 ,  H01L21/76224 ,  H10B12/02 ,  H10B12/485

Abstract: Systems, methods and apparatus are provided for damascene digit lines. For instance, a damascene digit line can be formed by forming a plurality of dummy digit lines on a semiconductor substrate that are separated by a first set of vertical trenches, depositing a sacrificial insulating material in the first set of vertical trenches, forming, and depositing an insulating fill material in, a second set of vertical trenches, forming, and depositing a nitride material in, nitride material deposition spaces; removing at least a portion of the semiconductor substrate to form plurality of cell contact deposition spaces, forming cell contacts in the cell contact deposition spaces, removing the dummy digit lines to form a plurality of vertical openings, removing nitride material to form expanded vertical opening, depositing a digit line insulating material in the expanded vertical openings to form digit line deposition spaces, and forming digit lines.

公开(公告)号：US20240079369A1

公开(公告)日：2024-03-07

申请号：US17938917

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Bret K. Street ,  Wei Zhou ,  Kyle K. Kirby ,  Amy R. Griffin ,  Thiagarajan Raman ,  Jaekyu Song

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/48 ,  H01L24/16 ,  H01L24/32 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48011 ,  H01L2224/4809 ,  H01L2224/48145 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438

Abstract: This document discloses techniques, apparatuses, and systems for connecting semiconductor dies through traces. A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die includes a first dielectric layer at which first circuitry is disposed. The second semiconductor die includes a second dielectric layer at which second circuitry is disposed. One or more traces extend from a side surface of the first dielectric layer and at a side surface of the second dielectric layer to electrically couple the first circuitry and the second circuitry. In doing so, rigid connective structures may not be needed to couple the first semiconductor die and the second semiconductor die.

公开(公告)号：US20240063207A1

公开(公告)日：2024-02-22

申请号：US17892038

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Terrence B. McDaniel ,  Amy R. Griffin ,  Kyle K. Kirby ,  Thiagarajan Raman

IPC: H01L25/00 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H10B80/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/34 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L21/568 ,  H01L24/11 ,  H01L24/80 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H10B80/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L23/345 ,  H01L23/3135 ,  H01L2221/68381 ,  H01L2221/68368 ,  H01L2224/0557 ,  H01L2224/06134 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/05555 ,  H01L2224/05571 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2224/80006

Abstract: Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a cavity configured to entrap a gas during the formation of the bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

公开(公告)号：US20240063094A1

公开(公告)日：2024-02-22

申请号：US17892034

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Kunal R. Parekh ,  Wei Zhou

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/13 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L25/0657 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/13 ,  H01L21/76898 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2224/73204 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L21/308

Abstract: A semiconductor device includes a semiconductor substrate including a cavity and a peripheral region surrounding the cavity. The peripheral region includes a first surface and a second surface opposite the first surface. The cavity extends from the first surface partially through the semiconductor substrate to a third surface. The third surface is parallel to the first surface and is located between the first surface and the second surface. The semiconductor device also includes a plurality of through-silicon vias (TSVs) extending between the first surface and the third surface.

公开(公告)号：US11282548B1

公开(公告)日：2022-03-22

申请号：US17307686

申请日：2021-05-04

Applicant: Micron Technology, Inc.

Inventor： Che-Chi Lee ,  Terrence B. McDaniel ,  Kehao Zhang ,  Albert P. Chan ,  Clement Jacob ,  Luca Fumagalli ,  Vinay Nair

IPC: G11C5/10 ,  H01L27/108 ,  H01L49/02 ,  G11C11/405 ,  H01L27/06

Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.