公开(公告)号：US20220013449A1

公开(公告)日：2022-01-13

申请号：US16925767

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Radhakrishna Kotti ,  David A. Kewley ,  Dave Pratt

IPC: H01L23/528 ,  H01L23/522

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

公开(公告)号：US20210375670A1

公开(公告)日：2021-12-02

申请号：US17444948

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Xiaosong Zhang ,  Yongjun J. Hu ,  David A. Kewley ,  Md Zahid Hossain ,  Michael J. Irwin ,  Daniel Billingsley ,  Suresh Ramarajan ,  Robert J. Hanson ,  Biow Hiem Ong ,  Keen Wah Chow

IPC: H01L21/768

Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.

公开(公告)号：US10388601B2

公开(公告)日：2019-08-20

申请号：US15842432

申请日：2017-12-14

Applicant: Micron Technology, Inc.

Inventor： William R. Brown ,  Jenna L. Russon ,  Tim H. Bossart ,  Brian R. Watson ,  Nikolay A. Mirin ,  David A. Kewley

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/11519 ,  G01R1/073 ,  G01R31/26 ,  H01L21/66 ,  H01L49/02 ,  H01L21/033 ,  H01L21/768 ,  H01L23/528 ,  H01L27/108 ,  H01L21/3213 ,  H01L27/11582

Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on each of the first conductive lines is on the enlarged portion thereof.

公开(公告)号：US20180114751A1

公开(公告)日：2018-04-26

申请号：US15842432

申请日：2017-12-14

Applicant: Micron Technology, Inc.

Inventor： William R. Brown ,  Jenna L. Russon ,  Tim H. Bossart ,  Brian R. Watson ,  Nikolay A. Mirin ,  David A. Kewley

IPC: H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/033 ,  H01L27/108

CPC classification number: H01L23/528 ,  G01R1/073 ,  G01R31/2601 ,  G06F17/5068 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76895 ,  H01L22/30 ,  H01L22/32 ,  H01L22/34 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/11519 ,  H01L27/11582 ,  H01L28/00

Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on the each of the first conductive lines is on the enlarged portion thereof.

公开(公告)号：US20170062324A1

公开(公告)日：2017-03-02

申请号：US14838768

申请日：2015-08-28

Applicant: Micron Technology, Inc.

Inventor： William R. Brown ,  Jenna L. Russon ,  Tim H. Bossart ,  Brian R. Watson ,  Nikolay A. Mirin ,  David A. Kewley

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5283 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/11582 ,  H01L28/00

Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on the each of the first conductive lines is on the enlarged portion thereof.

Abstract translation: 公开了一种包括导线的半导体器件。 第一导电线各自包括第一部分，第二部分和扩大部分，所述扩大部分连接第一导电线的第一部分和第二部分。 半导体器件包括第二导线，至少一些第二导线设置在一对第一导线之间，每个第二导线在第二导线的端部处包括比在其它部分的截面积更大的截面积 其中。 所述半导体器件包括在所述第一导线和所述第二导线中的每一个上的焊盘，其中，所述第二导线中的每一个上的所述焊盘位于所述第二导线的端部上， 部分。

公开(公告)号：US20160071878A1

公开(公告)日：2016-03-10

申请号：US14930504

申请日：2015-11-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Neal L. Davis ,  David A. Kewley

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

Abstract: Some embodiments include a semiconductor construction having a stack containing alternating levels of control gate material and intervening dielectric material. A channel material panel extends through the stack and along a first direction. The panel divides the stack into a first section on a first side of the panel and a second section on a second side of the panel. Memory cell stacks are between the channel material panel and the control gate material. The memory cell stacks include cell dielectric material shaped as containers having open ends pointing toward the channel material panel, and include charge-storage material within the containers. Some embodiments include methods of forming semiconductor constructions.

Abstract translation: 一些实施例包括具有堆叠的半导体结构，所述堆叠包含交替的控制栅极材料和中间介电材料。 通道材料面板沿着第一方向延伸穿过堆叠。 所述面板将所述堆叠分成所述面板的第一侧上的第一部分和所述面板的第二侧上的第二部分。 存储单元堆叠在通道材料面板和控制栅极材料之间。 存储单元堆叠包括形状为具有指向通道材料面板的开口端的容器的单元电介质材料，并且在容器内包括电荷存储材料。 一些实施例包括形成半导体结构的方法。

公开(公告)号：US09059115B2

公开(公告)日：2015-06-16

申请号：US14097003

申请日：2013-12-04

Applicant: Micron Technology, Inc.

Inventor： David A. Kewley ,  Brian Cleereman ,  Stephen W. Russell ,  Rex Stone ,  Anthony C. Krauth

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L21/32133 ,  H01L21/0337 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/32139 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

Abstract translation: 一些实施例包括形成存储器的方法。 可以在栅极堆叠上形成一系列光致抗蚀剂特征，并且可以在所述串联的末端形成占位符。 占位符可以通过间隙与所述系列的端部间隔开。 可以在光致抗蚀剂特征之上和之间在占位符上方以及在所述间隙内形成层。 该层可以沿光致抗蚀剂特征的边缘各向异性地蚀刻成多个第一垂直结构，并且沿着占位符的边缘进入第二垂直结构。 可以在第二垂直结构上形成掩模。 随后，可以使用第一垂直结构来模拟串门，同时使用掩模来对选择门进行图案化。 一些实施例包括形成导电流道的方法，并且一些实施例可以包括半导体结构。

公开(公告)号：US12178045B2

公开(公告)日：2024-12-24

申请号：US18158576

申请日：2023-01-24

Applicant: Micron Technology, Inc.

Inventor： Md Zakir Ullah ,  Xiaosong Zhang ,  Adam L. Olson ,  Mohammad Moydul Islam ,  Tien Minh Quan Tran ,  Chao Zhu ,  Zhigang Yang ,  Merri L. Carlson ,  Hui Chin Chong ,  David A. Kewley ,  Kok Siak Tang

IPC: H10B43/27 ,  H10B41/27

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. First and second arrays of pillars extend through the stack structure of the lower and upper decks, respectively. In one or more of the first and second pillar arrays, at least some pillars exhibit a greater degree of bending away from a vertical orientation than at least some other pillars. The pillars of the first array align with the pillars of the second array along an interface between the lower and upper decks. Related methods are also disclosed.

公开(公告)号：US20240282702A1

公开(公告)日：2024-08-22

申请号：US18652079

申请日：2024-05-01

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Radhakrishna Kotti ,  David A. Kewley ,  Dave Pratt

IPC: H01L23/528 ,  H01L23/522 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H10B61/00 ,  H10B63/84

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

公开(公告)号：US11990370B2

公开(公告)日：2024-05-21

申请号：US18048633

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76883 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/5283

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.