公开(公告)号：US07800153B2

公开(公告)日：2010-09-21

申请号：US12328046

申请日：2008-12-04

申请人： Yuichi Matsui ,  Masahiko Hiratani

发明人： Yuichi Matsui ,  Masahiko Hiratani

IPC分类号： H01L27/108

CPC分类号： H01L21/022 ,  C23C16/18 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02175 ,  H01L21/02183 ,  H01L21/02194 ,  H01L21/02271 ,  H01L21/02356 ,  H01L21/31604 ,  H01L21/31637 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/56 ,  H01L28/75 ,  H01L28/90

摘要： The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.

摘要翻译： 本发明涉及半导体电容器存储器件的电容器的结构，特别是五氧化二铌。 由于五氧化二铌具有600℃以下的低结晶温度，所以五氧化二铌可以通过热处理抑制底部电极和阻挡金属的氧化。 然而，根据低温热处理，从CVD源引入到膜中的碳不易氧化或除去。 因此，出现漏电流增加的问题。 作为电容器的绝缘膜，使用由五氧化二铌膜和五氧化钽膜构成的层叠膜或由五氧化二铌膜构成的层叠膜。 通过使用五氧化二铌膜，可以使电容器的介电常数高，可以降低结晶温度。 通过电介质膜的多级形成，可以降低泄漏电流。

公开(公告)号：US07728376B2

公开(公告)日：2010-06-01

申请号：US11723683

申请日：2007-03-21

申请人： Yuichi Matsui ,  Hiroshi Miki

发明人： Yuichi Matsui ,  Hiroshi Miki

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10852 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10894 ,  H01L28/91

摘要： HfO2 films and ZrO2 films are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant of such films may be increased by stabilizing their cubic phase. However, this results in an increase in the leakage current along the crystal grain boundaries, which makes it difficult to use these films as capacitor dielectric films. To overcome this problem, the present invention dopes a base material of HfO2 or ZrO2 with an oxide of an element having a large ion radius, such as Y or La, to increase the oxygen coordination number of the base material and thereby increase its relative dielectric constant to 30 or higher even when the base material is in its amorphous state. Thus, the present invention provides dielectric films that can be used to form DRAM capacitors that meet the 65 nm technology node or later.

摘要翻译： 目前，HfO2薄膜和ZrO2薄膜正在开发中用作85纳米技术节点DRAM中的电容器介质薄膜。 然而，这些膜将难以在65nm技术节点或之后的DRAM中使用，因为它们的相对介电常数只有20-25。 这些膜的介电常数可以通过稳定它们的立方相来增加。 然而，这导致沿着晶粒边界的漏电流的增加，这使得难以将这些膜用作电容器电介质膜。 为了克服这个问题，本发明通过具有大离子半径的元素的氧化物如Y或La掺杂HfO 2或ZrO 2的基材，以增加基材的氧配位数，从而增加其相对电介质 即使当基材处于其非晶态时，其也恒定在30或更高。 因此，本发明提供可用于形成满足65nm技术节点或更高版本的DRAM电容器的电介质膜。

公开(公告)号：US20100084698A1

公开(公告)日：2010-04-08

申请号：US12635181

申请日：2009-12-10

申请人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

发明人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

IPC分类号： H01L27/108

CPC分类号： H01L27/10852 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

公开(公告)号：US07408218B2

公开(公告)日：2008-08-05

申请号：US10488401

申请日：2001-12-14

申请人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

发明人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

IPC分类号： H01L27/108

CPC分类号： H01L27/10852 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

摘要翻译： DRAM的存储单元电容器（C 3）通过使用MIM电容器形成，该MIM电容器使用与逻辑电路（LOGIC）内的金属布线相同的层（M 3）的金属布线，从而使能 降低工艺成本。 通过使用高介电常数材料形成电容器并将其布置在其中形成位线（BL）的布线层上方，可以实现更高的积分。 此外，使用2T电池使得即使当它们以低电压工作时也可以提供足够的信号量。 通过对模拟（ANALOG）和存储器（MEM）中制造电容器的工艺进行通用化，可以以低成本在一个芯片上实现将逻辑，模拟和存储器安装在一起的半导体集成电路。

公开(公告)号：US07364965B2

公开(公告)日：2008-04-29

申请号：US10986497

申请日：2004-11-12

申请人： Osamu Tonomura ,  Hiroshi Miki ,  Yuichi Matsui ,  Tomoko Sekiguchi ,  Kikuo Watanabe

发明人： Osamu Tonomura ,  Hiroshi Miki ,  Yuichi Matsui ,  Tomoko Sekiguchi ,  Kikuo Watanabe

IPC分类号： H01L21/8242

CPC分类号： H01L21/02178 ,  H01L21/02181 ,  H01L21/02197 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/3141 ,  H01L21/3162 ,  H01L21/31645 ,  H01L27/1085 ,  H01L27/10855 ,  H01L28/65

摘要： A semiconductor device having a DRAM has a capacitor in which a dielectric film and an upper electrode are laminated on a lower electrode comprising a polysilicone, in which a natural oxide film oxidized by oxygen in the atmosphere grows to at least 1.5 nm on the surface of a lower electrode of the capacitor. Further, in forming the dielectric film, the dioxide film further grows in the case of using an oxidative raw material. This brings forth a reduction in capacitance, and an increase of a leakage current is caused.Therefore, after a dielectric film having a reduction property has been formed, the reduction property is promoted by a heat treatment to thereby reduce a dioxide film and realize making the dioxide film on the lower electrode surface thinner.

摘要翻译： 具有DRAM的半导体器件具有电容器，其中电介质膜和上电极层压在包含聚硅氧烷的下电极上，其中在大气中的氧气氧化的天然氧化物膜在其表面上生长至少至少1.5nm 电容器的下电极。 此外，在形成电介质膜时，在使用氧化性原料的情况下，二氧化硅膜进一步生长。 这导致电容的减小，并且引起漏电流的增加。 因此，在形成具有还原性的电介质膜之后，通过热处理促进还原性能，从而减少二氧化膜，实现使下电极表面上的二氧化物膜更薄。

公开(公告)号：US07112819B2

公开(公告)日：2006-09-26

申请号：US10829300

申请日：2004-04-22

申请人： Yuichi Matsui

发明人： Yuichi Matsui

IPC分类号： H01L29/786

CPC分类号： H01L28/56 ,  H01L21/02175 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02356 ,  H01L27/10852 ,  H01L28/55 ,  H01L28/65 ,  H01L28/90

摘要： A capacitor uses niobium pentoxide in the manufacture of a semiconductor device. The niobium pentoxide has a low crystallization temperature of 600° C. that provides control over the oxidation of the bottom electrode during heat-treatment. A dielectric constituent present as an amorphous oxide along the grain boundaries of polycrystalline niobium pentoxide is used for a capacitor insulator, thereby providing a method to decrease the leakage current along the grain boundary of niobium pentoxide and to realize a high dielectric constant and low-temperature crystallization.

摘要翻译： 电容器使用五氧化二铌制造半导体器件。 五氧化二铌具有600℃的低结晶温度，其在热处理期间提供对底部电极的氧化的控制。 作为电晶体绝缘体，使用沿着多晶铌五氧化物的晶界作为非晶形氧化物存在的电介质成分，从而提供减少沿着五氧化二铌的晶界的漏电流并实现高介电常数和低温的方法 结晶。

公开(公告)号：US20060027851A1

公开(公告)日：2006-02-09

申请号：US11242911

申请日：2005-10-05

申请人： Yuichi Matsui ,  Masahiko Hiratani

发明人： Yuichi Matsui ,  Masahiko Hiratani

IPC分类号： H01L29/94

CPC分类号： H01L21/022 ,  C23C16/18 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02175 ,  H01L21/02183 ,  H01L21/02194 ,  H01L21/02271 ,  H01L21/02356 ,  H01L21/31604 ,  H01L21/31637 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/56 ,  H01L28/75 ,  H01L28/90

摘要： The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of a niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.

摘要翻译： 本发明涉及半导体电容器存储器件的电容器的结构，特别是五氧化二铌。 由于五氧化二铌具有600℃以下的低结晶温度，所以五氧化二铌可以通过热处理抑制底电极和阻挡金属的氧化。 然而，根据低温热处理，从CVD源引入到膜中的碳不易氧化或除去。 因此，出现漏电流增加的问题。 作为电容器的绝缘膜，使用由五氧化二铌膜和五氧化二钽膜构成的层叠膜或由五氧化二铌膜构成的层叠膜。 通过使用五氧化二铌膜，可以使电容器的介电常数高，可以降低结晶温度。 通过电介质膜的多级形成，可以降低泄漏电流。

公开(公告)号：US06743739B2

公开(公告)日：2004-06-01

申请号：US10101600

申请日：2002-03-21

申请人： Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Yuichi Matsui ,  Toshihide Nabatame

发明人： Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Yuichi Matsui ,  Toshihide Nabatame

IPC分类号： H01L2131

CPC分类号： H01L28/60 ,  C23C16/18 ,  C23C16/409 ,  H01L21/28556 ,  H01L21/31604 ,  H01L27/10814 ,  H01L28/55

摘要： A process for forming the lower and upper electrodes of a high dielectric constant capacitor in a semiconductor device from an organoruthenium compound by chemical vapor deposition. This chemical vapor deposition technique employs an organoruthenium compound, an oxidizing gas, and a gas (such as argon) which is hardly adsorbed to the ruthenium surface or a gas (such as ethylene) which is readily adsorbed to the ruthenium surface. This process efficiently forms a ruthenium film with good conformality in a semiconductor device.

公开(公告)号：US06555429B2

公开(公告)日：2003-04-29

申请号：US09810627

申请日：2001-03-19

申请人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

发明人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/28562 ,  H01L27/10814

摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film. The upper and lower electrodes and an oxide dielectric film together constitute capacitors of the memory cells.

公开(公告)号：US06483143B2

公开(公告)日：2002-11-19

申请号：US09810401

申请日：2001-03-19

申请人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

发明人： Yuichi Matsui ,  Masahiko Hiratani ,  Yasuhiro Shimamoto ,  Yoshitaka Nakamura ,  Toshihide Nabatame

IPC分类号： H01L27108

CPC分类号： H01L28/60 ,  H01L21/28562 ,  H01L27/10814

摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film. The upper and lower electrodes and an oxide dielectric film together constitute capacitors of the memory cells.

摘要翻译： 在包括多个存储单元的半导体器件中，在形成有多个孔的层间绝缘膜上形成防沉积膜，或者在层间绝缘膜和内表面上选择性地形成晶种膜， 孔的底面。 在发生底层依赖性的条件下，通过化学气相沉积在沉积防止膜上或通过利用种子膜在层间绝缘膜上沉积Ru，Ir或Pt的膜。 因此，根据防沉积膜或种子膜的图案形成下部电极。 在预定温度下在下电极和防沉积膜上形成电介质膜。 即使暴露在用于形成电介质膜的预定温度下，下电极的材料也不会导通。 上电极进一步形成在电介质膜上。 上下电极和氧化物介质膜一起构成存储单元的电容器。