公开(公告)号：US20150263708A1

公开(公告)日：2015-09-17

申请号：US14723356

申请日：2015-05-27

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  Ge Yang

IPC: H03K3/3562 ,  H03K3/012

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372

Abstract: A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

公开(公告)号：US20150222266A1

公开(公告)日：2015-08-06

申请号：US14170342

申请日：2014-01-31

Applicant: Nvidia Corporation

Inventor： Hwong-Kwo Lin ,  Ge Yang ,  Xi Zhang ,  Ying Huang

IPC: H03K19/003 ,  G06F1/10 ,  H03K3/037

CPC classification number: H03K19/003 ,  G06F1/10 ,  H03K3/0372

Abstract: A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF).

Abstract translation: 触发器和从异步域接收数字信号的方法。 在一个实施例中，触发器包括：（1）耦合到触发器输入并具有第一和第二稳定状态的第一环路和（2）耦合到第一环路并具有第一和第二稳定状态的第二环路 在第一和第二回路中的交叉耦合的反相器的特性产生亚稳态，其在第一回路中朝向第一稳定状态倾斜，并且朝向第二回路中的第二稳定状态倾斜。 触发器的某些实施例具有较低的时间常数，因此具有较高的平均故障间隔时间（MTBF）。

公开(公告)号：US20140169108A1

公开(公告)日：2014-06-19

申请号：US13715991

申请日：2012-12-14

Applicant: NVIDIA CORPORATION

Inventor： Ge Yang ,  Hwong-Kwo Lin ,  Xi Zhang ,  Jiani Yu ,  Haiyan Gong

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C11/4091

Abstract: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.

Abstract translation: 减轻对长信号线的外部影响。 根据本发明的实施例，存储阵列的列包括被配置为上拉列的位线的第一和第二晶体管。 该列包括第三晶体管，其被配置为响应于该列的反相位线的电平有选择地上拉该列的位线;以及第四晶体管，其被配置为响应于该列的反相位线选择性地上拉该反相位线 列的位线。 该列还包括第五和第六晶体管，其被配置为响应钳位信号选择性地上拉该列的位线和反相位线;以及第七晶体管，被配置为选择性地耦合该列的位线和该列的反相位线 响应钳位信号。

公开(公告)号：US09484115B1

公开(公告)日：2016-11-01

申请号：US14711712

申请日：2015-05-13

Applicant: NVIDIA CORPORATION

Inventor： Stephen Felix ,  Hwong-Kwo Lin ,  Spencer Gold ,  Jing Guo ,  Andreas Gotterba ,  Jason Golbus ,  Karthik Natarajan ,  Jun Yang ,  Zhenye Jiang ,  Ge Yang ,  Lei Wang ,  Yong Li ,  Hua Chen ,  Haiyan Gong ,  Beibei Ren ,  Eric Voelkel

IPC: G11C29/08 ,  G11C11/16 ,  G11C7/00 ,  G11C5/14

CPC classification number: G11C11/1697 ,  G11C5/143 ,  G11C7/00 ,  G11C11/417 ,  G11C29/08 ,  G11C2207/2227

Abstract: A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.

Abstract translation: 被配置为选择对静态随机存取存储器单元的电源的子系统将专用存储器电源电压的电平与主系统电源电压进行比较。 当系统电压高于具有一定余量的存储器电源电压时，子系统将主系统电源切换到SRAM单元。 当系统电压低于存储器电源电压时，子系统将存储器电源切换到SRAM单元。 当系统电压与存储器电源相当时，如果性能是优先考虑的话，子系统将系统电压切换到SRAM单元，但如果降低功耗是优先考虑的话，将存储器电源切换到SRAM单元。 以这种方式，系统实现最佳性能而不会导致稳态功率损耗，并避免访问存储器时的定时问题。

公开(公告)号：US09071233B2

公开(公告)日：2015-06-30

申请号：US13949252

申请日：2013-07-24

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  Ge Yang

IPC: H03K3/289 ,  H03K3/356 ,  H03K3/037

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372

Abstract: A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

Abstract translation: 触发器电路可以包括主锁存器和从锁存器。 每个锁存器可以具有透明模式和存储模式。 当主锁存器处于透明模式时，从锁存器可能处于存储模式; 反之亦然。 时钟信号可以通过一对时钟门控上拉晶体管和一对时钟门控的下拉晶体管来控制每个锁存器的模式，总共四个时钟门控晶体管。 时钟门控晶体管可以由主锁存器和从锁存器共享。 当共享时，可能需要更少的时钟门控晶体管，而不是被共享。 由于寄生电容的充电和放电，时钟门控晶体管可能具有寄生电容并且当经受变化的时钟信号时消耗功率。 因此，具有更少的时钟门控晶体管可以减少触发器电路消耗的功率。

公开(公告)号：US20140125377A1

公开(公告)日：2014-05-08

申请号：US13668110

申请日：2012-11-02

Applicant: NVIDIA CORPORATION

Inventor： Hwong-Kwo Lin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Ting-Hsiang Chu

IPC: H03K19/0175 ,  H03K19/00

CPC classification number: H03K3/356156 ,  G01R31/318541 ,  H03K3/356121

Abstract: A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.

Abstract translation: 双触发器电路将两个或更多个触发器子电路组合成单个电路。 触发器电路包括第一触发器子电路和第二触发器子电路。 第一触发器子电路包括第一存储子电路，其被配置为存储第一选择的输入信号，并且当缓冲的时钟信号在两个不同逻辑电平之间转换时，将第一选定的输入信号传送到第一输出信号， 被配置为接收时钟输入信号，产生反相时钟信号，并产生缓冲的时钟信号。 第二触发器子电路耦合到时钟驱动器并且被配置为接收反相时钟信号和经缓冲的时钟信号。 第二触发器子电路包括第二存储子电路，其被配置为存储第二选择的输入信号，并且在缓冲的时钟信号转换时将第二选定的输入信号传送到第二输出信号。

公开(公告)号：US20140122949A1

公开(公告)日：2014-05-01

申请号：US13663379

申请日：2012-10-29

Applicant: NVIDIA CORPORATION

Inventor： Ilyas Elkin ,  Ge Yang

IPC: G01R31/3177

CPC classification number: G01R31/318541 ,  G01R31/28 ,  G01R31/3177 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318572

Abstract: Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

Abstract translation: 介绍了锁存器的系统和方法。 在一个实施例中，系统包括传播组件，数据传播组件和控制组件中的扫描。 传播分量中的扫描可操作以在数值扫描和再循环值之间进行选择。 数据传播组件可操作以在数据值和从传播组件中的扫描转发的结果之间进行选择，其中数据传播组件的结果作为再循环值被转发到传播组件中的扫描。 控制组件可操作以通过传播组件和数据传播组件中的扫描来控制选择的指示。

公开(公告)号：US08604855B2

公开(公告)日：2013-12-10

申请号：US13921138

申请日：2013-06-18

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  Ge Yang

IPC: H03K3/356

CPC classification number: H03K3/36 ,  H03K3/012 ,  H03K3/356121

Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

Abstract translation: 本发明的一个实施例提出了一种技术，用于使用完全静态且对制造工艺变化不敏感的双触发低能量触发器电路来捕获和存储输入信号电平的技术。 双触发低能触发器电路仅向时钟信号提供三个晶体管栅极负载，并且当输入信号保持恒定时，内部节点都不会切换。 时钟信号之一可以是低频“保持时钟”，其比输入到两个晶体管栅极的另外两个时钟信号频率更低。 输出信号Q在上升时钟沿使用分离的触发子电路设置或复位。 当时钟信号为低电平时，设置或复位可以布防，并且在时钟的上升沿触发置位或复位。