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公开(公告)号：US10014878B1
公开(公告)日：2018-07-03
申请号：US15849672
申请日：2017-12-21
Applicant: NXP B.V.
Inventor： Lucien Johannes Breems , Muhammed Bolatkale
Abstract: A data processor is disclosed. The data processor includes a data processing module. The data processing modules includes an input for receiving an input signal, an output for providing a quantized output signal, a combining unit configured to combine a feedback signal from the output with the input signal and a quantizer configured to provide the quantized output signal based on the combined signal. The data processor further includes a correction module configured to receive the quantized output signal, generate a full-scale digital signal based on the quantized output signal, determine a metastability error in the full-scale digital signal and provide a compensated output signal based on the quantized output signal and the determined metastability error.
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公开(公告)号：US09906384B1
公开(公告)日：2018-02-27
申请号：US15275968
申请日：2016-09-26
Applicant: NXP B.V.
Inventor： Robert Rutten , Lucien Johannes Breems , Johannes Hubertus Antonius Brekelmans , Jan Niehof , Muhammed Bolatkale , Shagun Bajoria
IPC: H04L25/03
CPC classification number: H04L25/03885 , H03D3/009 , H04L27/3863 , H04L2025/0349 , H04L2025/03808
Abstract: Corrections are provided for mismatches between an in-phase (I) signal and a quadrature-phase (Q) signal, the I and Q signals having a first frequency band. A frequency filter circuit filters the I and Q signals to produce a filtered I and Q output with a second frequency band that is a subset of the first frequency band. Digital circuitry includes a multiple-tap correction filter having a plurality of taps and configured to generate I and Q output signals by filtering the I and Q signals according to respective sets of coefficients for the plurality of taps. A coefficient estimator generates the sets of coefficients relative to different frequency bands.
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公开(公告)号：US12126351B2
公开(公告)日：2024-10-22
申请号：US18061601
申请日：2022-12-05
Applicant: NXP B.V.
Inventor： Robert Rutten , Muhammed Bolatkale , Lucien Johannes Breems
CPC classification number: H03M1/0621 , H03M1/1047 , H03M1/181 , H03M1/1009 , H03M1/68
Abstract: Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal. Hereby, the digital inputs provided to the DACs are non-randomized.
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公开(公告)号：US12015426B2
公开(公告)日：2024-06-18
申请号：US17880868
申请日：2022-08-04
Applicant: NXP B.V.
Inventor： Lucien Johannes Breems , Muhammed Bolatkale
IPC: H03M3/00
CPC classification number: H03M3/354
Abstract: A delta-sigma modulator including force circuitry that receives an output digital signal and provides a forced digital signal with a predetermined force state based on a force control signal, a combiner that subtracts the forced digital signal from the output digital signal for providing a digital error signal, and force correction circuitry that converts the digital error signal into one or more analog error correction signals applied to corresponding inputs of loop filter circuitry. The digital error signal and the force control signal may each be used to develop corresponding analog feedback signals used to adjust an analog input signal. The digital error signal may also be converted to one or more correction signals applied to corresponding inputs of the loop filter circuitry to correct the output digital signal. The digital error signal may also be used by a digital noise cancellation filter to further correct the output digital signal.
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25.发明公开公开(公告)号：US20240048146A1
公开(公告)日：2024-02-08
申请号：US18357689
申请日：2023-07-24
Applicant: NXP B.V.
Inventor： Shagun Bajoria , Muhammed Bolatkale , Lucien Johannes Breems , Robert Rutten , Mohammed Abo Alainein
IPC: H03M1/06
CPC classification number: H03M1/0602
Abstract: A circuit 100 is described comprising (i) a first digital-to-analog converter 110, (ii) a second digital-to-analog converter 111, (iii) a plurality of unit elements 120, and (iv) switching circuitry 130. The switching circuitry 130 is adapted so that in a first switching state 231, a set of unit elements 221 of the plurality of unit elements 120 forms part of the first digital-to-analog converter 110, and in a second switching state 232, the set of unit elements 221 forms part of the second digital-to-analog converter 111. Furthermore, a corresponding method of operating a circuit 100 is described.
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Patent Agency Ranking
公开(公告)号：US11876524B2
公开(公告)日：2024-01-16
申请号：US17809315
申请日：2022-06-28
Applicant: NXP B.V.
Inventor： Muhammed Bolatkale
CPC classification number: H03M1/001 , H03M1/0629 , H03M1/00 , H03M1/12 , H03M3/00
Abstract: There is described a hybrid ADC device for converting an analog input signal (Vin) into a digital output signal (Vout), the device comprising a first ADC circuit configured to receive the analog input signal (Vin) and convert it into a first digital signal (Y0); a DAC circuit configured to receive the first digital signal and convert it into a first analog signal; a delay circuit configured to delay the analog input signal; a first combiner configured to generate an analog residual signal by subtracting the first analog signal from the delayed analog input signal; a second ADC circuit configured to receive the residual analog signal and convert it into a second digital signal (Y1); a filter circuit configured to receive the first digital signal and output a filtered first digital signal (Y0′), the filter circuit having a transfer function corresponding to a combined transfer function of the DAC circuit and the second ADC circuit; and a second combiner configured to generate the digital output signal (Vout) by adding the second digital signal and the filtered first digital signal, wherein the first ADC circuit comprises an anti-aliasing filter. Furthermore, a corresponding method and an automobile radar system are described.
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公开(公告)号：US20230361781A1
公开(公告)日：2023-11-09
申请号：US18310184
申请日：2023-05-01
Applicant: NXP B.V.
Inventor： Muhammed Bolatkale , Lucien Johannes Breems , Pierluigi Cenci , Shagun Bajoria , Mohammed Abo Alainein
Abstract: There is described an analog-to-digital converter, ADC, device (100), comprising:
i) a first converter stage (110), comprising a first digital-to-analog converter, DAC, (115), comprising at least two first unit elements (116, 117, 118) each with a first unit element value (U11, U12, U13);
ii) a second converter stage (120), comprising a second DAC (125), comprising at least two second unit elements each with a second unit element value (U21, U22, U23); and
iii) a control device (180), coupled to the first DAC (115) and the second DAC and configured to:
swap at least one of the first unit element values (U1) with at least one of the second unit element values (U2) to obtain corresponding third unit element values (U3) and forth unit element values (U4).-
28.发明授权公开(公告)号：US11463101B2
公开(公告)日：2022-10-04
申请号：US17158913
申请日：2021-01-26
Applicant: NXP B.V.
Inventor： Chenming Zhang , Lucien Johannes Breems , Muhammed Bolatkale
IPC: H03M3/00
Abstract: The present disclosure relates generally to techniques for continuous-time sigma-delta analog-to-digital converter (ADC). The continuous-time sigma-delta ADC may include a feed-forward capacitor in parallel with a current-steering excess loop delay (ELD) digital-to-analog converter (DAC), and by creating a zero in a transfer function of a Gm cell, both an ELD feedback loop settling and a main feedback loop may be recovered. As a result, the performance and stability of the continuous-time sigma-delta ADC can be achieved. Additionally, a summation node in the continuous-time sigma-delta ADC may offer flexibility in the architecture design of the continuous-time sigma-delta ADC.
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公开(公告)号：US20170317860A1
公开(公告)日：2017-11-02
申请号：US15481038
申请日：2017-04-06
Applicant: NXP B.V.
Inventor： Muhammed Bolatkale , Lucien Johannes Breems
CPC classification number: H04L25/08 , H03M1/001 , H03M1/1009 , H04B1/0007 , H04B1/109 , H04B1/123
Abstract: A receiver circuit comprising: an input terminal configured to receive an input-signal; a feedforward-ADC configured to provide a feedforward-digital-signal based on the input-signal; a feedforward-DAC configured to provide a feedforward-analogue-signal based on the feedforward-digital-signal; a feedforward-subtractor configured to provide an error-signal based on the difference between the feedforward-analogue-signal and the input-signal; an error-LNA configured to provide an amplified-error-signal based on the error-signal; an error-ADC configured to provide a digital-amplified-error-signal based on the amplified-error-signal; a mixer configured to down-convert a signal in a signal path between the input terminal and the error-ADC; and an error-cancellation-block configured to provide an error-cancelled-signal based on a difference between the digital-amplified-error-signal and the feedforward-digital-signal.
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公开(公告)号：US09712184B2
公开(公告)日：2017-07-18
申请号：US15197398
申请日：2016-06-29
Applicant: NXP B.V.
Inventor： Lucien Johannes Breems , Muhammed Bolatkale
IPC: H03M3/00
CPC classification number: H03M3/422 , H03M3/376 , H03M3/42 , H03M3/452 , H03M3/454 , H03M3/464 , H03M3/50
Abstract: A sigma-delta modulator comprising a plurality of filter stages in series with each other, wherein at least one of the plurality of filter stages is configured to provide a filter-output-signal; and a plurality of gain stages, each gain stage configured to provide a gain-output-signal. The sigma-delta modulator also includes a filter-output-switching-element configured to selectively couple the filter-output-signal to an input terminal of one of the plurality of gain stages; and a plurality of filter-input-switching-elements. Each of the plurality of filter-input-switching-elements is associated with one of the plurality of filter stages, wherein the plurality of filter-input-switching-elements are configured to selectively couple one of the gain-stage-output-signals to an input terminal of its associated one of the plurality of filter stages.
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