公开(公告)号：US06660585B1

公开(公告)日：2003-12-09

申请号：US09531787

申请日：2000-03-21

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Vei-Han Chan ,  Hung-Sheng Chen ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Vei-Han Chan ,  Hung-Sheng Chen ,  Fu-Chang Hsu

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  G11C16/0416 ,  H01L21/28273

摘要： In this invention a stacked gate flash memory cell is disclosed which has a lightly doped drain (LDD) on the drain side of the device and uses the source to both program using hot electron generation and erase the floating gate using Fowler-Nordheim-tunneling. Disturb conditions are reduced by taking advantage of the LDD and the biasing of the cell that uses the source for both programming and erasure. The electric field of the drain is greatly reduced as a result of the LDD which reduces hot electron generation. The LDD also helps reduce bit line disturb conditions during programming. A transient bit line disturb condition in a non-selected cell is minimized by preconditioning the bit line to the non-selected cell to Vcc.

摘要翻译： 在本发明中，公开了一种堆叠栅极闪存单元，其在器件的漏极侧具有轻掺杂漏极（LDD），并且使用源使用热电子发生进行编程并使用Fowler-Nordheim隧道擦除浮动栅极。 通过利用LDD和使用源进行编程和擦除的单元的偏置来减少干扰条件。 作为减少热电子产生的LDD的结果，漏极的电场大大减小。 LDD还有助于在编程期间减少位线干扰条件。 通过将未选择的单元的位线预处理为Vcc，使未选择的单元中的瞬态位线干扰条件最小化。

公开(公告)号：US06584034B1

公开(公告)日：2003-06-24

申请号：US10131271

申请日：2002-04-23

申请人： Fu-Chang Hsu ,  Peter W. Lee ,  Hsing-Ya Tsao

发明人： Fu-Chang Hsu ,  Peter W. Lee ,  Hsing-Ya Tsao

IPC分类号： G11C800

CPC分类号： G11C16/10 ,  G11C7/18 ,  G11C8/12 ,  G11C2216/22

摘要： In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.

摘要翻译： 在本发明中公开了一种用于同时读和写操作的闪速存储器。 存储器被划分成多个扇区，每个扇区具有扇区解码器。 扇区解码器将多个主位线连接到每个存储器扇区内所包含的多个子位线。虽然可以使用包括2M解码器和分层式解码器的其他解码器，但是使用解码器来解释本发明。 存储器阵列可以由各种架构进行配置，包括NOR，OR，NAND，AND，Dual-String和DINOR。 存储器单元可以由包括ETOX，FLOTOX，EPROM，EEPROM，分离栅极和PMOS的各种阵列结构形成。

公开(公告)号：US5796657A

公开(公告)日：1998-08-18

申请号：US691281

申请日：1996-08-01

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

IPC分类号： G11C8/08 ,  G11C8/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  H01L27/115 ,  G11C16/00

CPC分类号： G11C8/08 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0416 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3413 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C8/10 ,  H01L27/115 ,  G11C16/24 ,  G11C2211/5642 ,  G11C2211/5644 ,  G11C2216/20 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/00 ,  G11C8/14

摘要： A flash memory with a flexible erasing size includes a first bank of flash transistors and a second bank of flash transistors. Each bank of flash transistors forms a plurality of rows and a plurality of columns, each transistor having a gate, drain and source, where the gates of transistors in each row are coupled to common wordlines, the drains of transistors in each column are coupled to common bitlines and the sources of the transistors in the first bank are all coupled to a first sourceline and the sources of the transistors in the second bank are all coupled to a second sourceline. A wordline decoder is coupled to the wordlines and configured to receive a wordline address signal and to decode the wordline address signal to select a wordline, where the wordline decoder includes a wordline latch configured to latch the selected wordline. A sourceline decoder is coupled to the sourcelines and configured to receive a sourceline address signal and to decode the sourceline address signal to select a sourceline, where the sourceline decoder includes a sourceline latch configured to latch the selected sourceline. A bitline decoder is coupled to the bitlines and configured to receive a bitline address signal and to decode the bitline address signal to latch a selected bitline, where the bitline decoder includes a bitline latch configured to latch the selected bitline.

摘要翻译： 具有柔性擦除尺寸的闪速存储器包括闪存晶体管的第一组和闪存晶体管的第二组。 每个闪存晶体管组形成多个行和多个列，每个晶体管具有栅极，漏极和源极，其中每行中的晶体管的栅极耦合到公共字线，每列中的晶体管的漏极耦合到 公共位线和第一组中的晶体管的源极都耦合到第一源极线，并且第二组中的晶体管的源极都耦合到第二源极线。 字线解码器被耦合到字线并被配置为接收字线地址信号并且解码字线地址信号以选择字线，其中字线解码器包括配置成锁存所选字线的字线锁存器。 源线解码器被耦合到源极线并且被配置为接收源线地址信号并且解码源线地址信号以选择源极线，其中源极线解码器包括被配置为锁存所选择的源极线的源极线锁存器。 位线解码器耦合到位线并且被配置为接收位线地址信号并且解码位线地址信号以锁存所选择的位线，其中位线解码器包括被配置为锁存所选位线的位线锁存器。

公开(公告)号：US5768193A

公开(公告)日：1998-06-16

申请号：US745034

申请日：1996-11-07

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

IPC分类号： G11C8/08 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/115 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0416 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3413 ,  G11C16/3431 ,  G11C8/08 ,  H01L27/115 ,  G11C16/08 ,  G11C16/24 ,  G11C2211/5644 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/00 ,  G11C8/14

摘要： In a method and circuit for refreshing a flash memory with a memory array, data corresponding to that stored in a memory cell of the memory array is read by applying a read voltage thereto. Thereafter, an erase verify voltage lower than the read voltage is applied to the memory array, and conduction of the memory cell is sensed. Based on non-conduction of the memory cell and the data of the memory cell, the memory cell is selectively discharged to compensate for undesired charge gain. Subsequently, a program verify voltage higher than the read voltage is applied to the memory array, and conduction of the memory cell is sensed. Based on conduction of the memory cell and the data of the memory cell, the memory cell is selectively charged to compensate for undesired charge loss. A method and circuit for initiating the refresh operation automatically is also disclosed.

摘要翻译： 在用存储器阵列刷新闪速存储器的方法和电路中，通过对存储器阵列的存储单元中存储的读取电压来读取对应于存储器阵列的存储单元的数据。 此后，将低于读取电压的擦除验证电压施加到存储器阵列，并且感测存储器单元的导通。 基于存储器单元的非导通和存储单元的数据，存储单元被选择性地放电以补偿不期望的电荷增益。 随后，将高于读取电压的程序验证电压施加到存储器阵列，并且感测存储器单元的导通。 基于存储器单元的传导和存储单元的数据，存储单元被选择性地充电以补偿不期望的电荷损失。 还公开了一种自动启动刷新操作的方法和电路。

公开(公告)号：US5687121A

公开(公告)日：1997-11-11

申请号：US645630

申请日：1996-05-14

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

IPC分类号： G11C8/10 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G11C16/00

CPC分类号： G11C8/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5642 ,  G11C2216/20 ,  G11C8/00

摘要： A flash memory wordline decoder includes a plurality of voltage terminals to receive a plurality of voltages, a plurality of address terminals to receive a plurality of address signals, a procedure terminal to receive a procedure signal, and a plurality of output wordlines adapted to be coupled to a bank of flash transistors. The wordline decoder circuit is configured to decode the address signals and includes latches coupled to the wordlines, where the latches are configured to latch the wordlines and to provide an operational voltage on the wordline to accomplish a predetermined operation responsive to the procedure signal. Advantages of the invention include a verification with a low verification voltage such as 1 V or less for operating with a VDD supply voltage as low as 1.5 V. The decoder also reduces erase/write cycle time and improves expected lifetime of the flash memory due to reduced stress on the flash transistors within the flash memory.

摘要翻译： 闪存字线解码器包括多个用于接收多个电压的电压端子，多个地址端子以接收多个地址信号，用于接收过程信号的过程终端，以及适于耦合的多个输出字线 到一组闪存晶体管。 字线解码器电路被配置为对地址信号进行解码并且包括耦合到字线的锁存器，其中锁存器被配置为锁存字线并且在字线上提供操作电压以响应于过程信号来完成预定操作。 本发明的优点包括使用诸如1V或更低的验证电压的验证，用于以低至1.5V的VDD电源电压工作。解码器还减少了擦除/写入周期时间并且改善了闪存的预期寿命，这是由于 闪存中的闪存晶体管的应力减小。

公开(公告)号：US20110170357A1

公开(公告)日：2011-07-14

申请号：US13072281

申请日：2011-03-25

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC分类号： G11C16/04

CPC分类号： H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

摘要翻译： 公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。 此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。 与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。 此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

公开(公告)号：US07289366B2

公开(公告)日：2007-10-30

申请号：US11376076

申请日：2006-03-15

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L27/115 ,  H01L27/11524

摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

公开(公告)号：US06850438B2

公开(公告)日：2005-02-01

申请号：US10351179

申请日：2003-01-24

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

IPC分类号： G11C16/04 ,  G11C16/14 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3445 ,  G11C2216/18 ,  G11C2216/22 ,  H01L27/11521 ,  H01L27/11524

摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

公开(公告)号：US06788612B2

公开(公告)日：2004-09-07

申请号：US10423559

申请日：2003-04-25

申请人： Fu-Chang Hsu ,  Peter W. Lee ,  Hsing-Ya Tsao

发明人： Fu-Chang Hsu ,  Peter W. Lee ,  Hsing-Ya Tsao

IPC分类号： G11C800

CPC分类号： G11C16/10 ,  G11C7/18 ,  G11C8/12 ,  G11C2216/22

摘要： In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.

公开(公告)号：US06620682B1

公开(公告)日：2003-09-16

申请号：US09978230

申请日：2001-10-16

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Mervyn Wong

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Mervyn Wong

IPC分类号： H01L21336

CPC分类号： G11C16/3404 ,  G11C16/0416 ,  G11C16/344 ,  H01L27/115 ,  H01L29/66825

摘要： In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.

摘要翻译： 在本发明中，示出了在NOR型EEPROM闪速存储器阵列的存储单元操作中使用三个并行字线电压的方法。 第一并行字线电压控制在所选择的存储器块内的选定字线上的操作。 第二并发字线电压抑制所选存储块中未选择的字线上的单元，并且第三并发字线电压抑制未被选择的块中的未选择的单元从干扰条件。 此外，三个连续的字线电压允许块被擦除，块内的页被擦除，并且块内的页被禁止进一步擦除。 三个连续的电压还允许检测电池的过度擦除，基于页面的校正，以及验证校正的单元的阈值电压是否高于擦除值但低于擦除值。 本文描述的方法产生具有窄电压分布的电池阈值电压。