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    Camera control interface extension bus
    23.
    发明授权
    Camera control interface extension bus 有权
    相机控制接口扩展总线

    公开(公告)号：US09552325B2

    公开(公告)日：2017-01-24

    申请号：US14302362

    申请日：2014-06-11

    Applicant: QUALCOMM Incorporated

    Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

    IPC: G06F13/42 ,  G06F13/364 ,  H04L7/033

    CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  H04L7/0331

    Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

    Abstract translation: 描述了提供用于内部集成电路（I2C）和/或相机控制接口（CCI）操作的串行总线的改进的性能的系统，方法和装置。 描述CCI扩展（CCIe）设备。 CCIe设备可以配置为总线主机或从机。 在一种方法中，CCIe发射机可以从一组比特生成转换号码，将转换号码转换为符号序列，并以两线串行总线的信令状态发送符号序列。 定时信息可以在符号序列中的连续符号对符号之间的转换中被编码。 例如，每个转换可能导致两线串行总线的至少一根线的信令状态改变。 CCIe接收机可以从转换中导出接收时钟，以便接收和解码符号序列。

    MULTI-WIRE OPEN-DRAIN LINK WITH DATA SYMBOL TRANSITION BASED CLOCKING
    24.
    发明申请
    MULTI-WIRE OPEN-DRAIN LINK WITH DATA SYMBOL TRANSITION BASED CLOCKING 有权
    多线打开链接与数据符号转换的时钟

    公开(公告)号：US20160261400A1

    公开(公告)日：2016-09-08

    申请号：US15156555

    申请日：2016-05-17

    Applicant: QUALCOMM Incorporated

    Inventor： Shoichiro Sengoku ,  Joseph Cheung ,  George Alan Wiley

    IPC: H04L7/00 ,  H04L7/033

    CPC classification number: H04L7/0087 ,  H03K3/017 ,  H03K5/13 ,  H03K5/133 ,  H03K5/134 ,  H03K5/14 ,  H03K5/153 ,  H03K5/1534 ,  H03K19/00 ,  H03K2005/00293 ,  H03L7/081 ,  H04L7/0037 ,  H04L7/033 ,  H04L7/0331

    Abstract: A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.

    Abstract translation: 描述了一种方法，装置和计算机程序产品。 该装置通过确定从多线开漏链路接收的信号中的转变来产生用于从多线开漏链路接收数据的接收时钟信号，响应于该转换产生时钟脉冲，延迟时钟脉冲 如果转换处于第一方向，则通过预先配置的第一间隔，并且如果转换处于第二方向，则将时钟延迟预先配置的第二间隔。 基于与通信接口相关联的上升时间和/或下降时间来配置预配置的第一和/或第二间隔，并且可以通过测量与为第一和第二校准转换产生的时钟脉冲相关联的相应延迟来校准预配置的第一和/或第二间隔。

    Multi-wire open-drain link with data symbol transition based clocking
    25.
    发明授权
    Multi-wire open-drain link with data symbol transition based clocking 有权
    多线开漏链路，具有基于数据符号转换的时钟

    公开(公告)号：US09374216B2

    公开(公告)日：2016-06-21

    申请号：US14220056

    申请日：2014-03-19

    Applicant: QUALCOMM Incorporated

    Inventor： Shoichiro Sengoku ,  Joseph Cheung ,  George Alan Wiley

    IPC: H04L7/033 ,  H03K5/1534 ,  H03K3/017 ,  H03K5/153 ,  H03L7/081 ,  H03K5/13 ,  H03K5/134 ,  H03K19/00 ,  H03K5/14 ,  H03K5/00 ,  H04L7/00

    CPC classification number: H04L7/0087 ,  H03K3/017 ,  H03K5/13 ,  H03K5/133 ,  H03K5/134 ,  H03K5/14 ,  H03K5/153 ,  H03K5/1534 ,  H03K19/00 ,  H03K2005/00293 ,  H03L7/081 ,  H04L7/0037 ,  H04L7/033 ,  H04L7/0331

    Abstract: A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.

    Abstract translation: 描述了一种方法，装置和计算机程序产品。 该装置通过确定从多线开漏链路接收的信号中的转变来产生用于从多线开漏链路接收数据的接收时钟信号，响应于该转换产生时钟脉冲，延迟时钟脉冲 如果转换处于第一方向，则通过预先配置的第一间隔，并且如果转换处于第二方向，则将时钟延迟预先配置的第二间隔。 基于与通信接口相关联的上升时间和/或下降时间来配置预配置的第一和/或第二间隔，并且可以通过测量与为第一和第二校准转换产生的时钟脉冲相关联的相应延迟来校准预配置的第一和/或第二间隔。

    CAMERA CONTROL INTERFACE EXTENSION BUS
    27.
    发明申请
    CAMERA CONTROL INTERFACE EXTENSION BUS 有权
    摄像机控制界面扩展总线

    公开(公告)号：US20140372643A1

    公开(公告)日：2014-12-18

    申请号：US14302362

    申请日：2014-06-11

    Applicant: QUALCOMM Incorporated

    Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

    IPC: G06F13/42

    CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4295 ,  H04L7/0331

    Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

    Abstract translation: 描述了提供用于内部集成电路（I2C）和/或相机控制接口（CCI）操作的串行总线的改进的性能的系统，方法和装置。 描述CCI扩展（CCIe）设备。 CCIe设备可以配置为总线主机或从机。 在一种方法中，CCIe发射机可以从一组比特生成转换号码，将转换号码转换为符号序列，并以两线串行总线的信令状态发送符号序列。 定时信息可以在符号序列中的连续符号对符号之间的转换中被编码。 例如，每个转换可能导致两线串行总线的至少一根线的信令状态改变。 CCIe接收机可以从转换中导出接收时钟，以便接收和解码符号序列。

    EFFICIENT N-FACTORIAL DIFFERENTIAL SIGNALING TERMINATION NETWORK
    29.
    发明申请
    EFFICIENT N-FACTORIAL DIFFERENTIAL SIGNALING TERMINATION NETWORK 有权
    有效的N-FACICE差分信令终止网络

    公开(公告)号：US20140254711A1

    公开(公告)日：2014-09-11

    申请号：US13832990

    申请日：2013-03-15

    Applicant: QUALCOMM INCORPORATED

    Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

    IPC: H03H2/00 ,  H04B1/04

    CPC classification number: H03H2/005 ,  H04B1/04 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/14 ,  Y02D30/30

    Abstract: A termination network circuit for a differential signal transmitter comprises a plurality of n resistance elements and a plurality of differential signal drivers. A first end of each of the resistance elements is coupled at a common node, where n is an integer value and is the number of conductors used to transmit a plurality of differential signals. Each differential signal driver may include a positive terminal driver and a negative terminal driver. The positive terminal driver is coupled to a second end of a first resistance element while the negative terminal driver is coupled to a second end of a second resistance element. The positive terminal driver and the negative terminal driver are separately and independently switchable to provide a current having a magnitude and direction. During a transmission cycle each of the resistance elements has a current of a different magnitude and/or direction than the other resistance elements.

    Abstract translation: 用于差分信号发射机的终端网络电路包括多个n个电阻元件和多个差分信号驱动器。 每个电阻元件的第一端在公共节点处耦合，其中n是整数值，并且是用于发送多个差分信号的导体的数量。 每个差分信号驱动器可以包括正极端子驱动器和负极端子驱动器。 正端子驱动器耦合到第一电阻元件的第二端，而负端子驱动器耦合到第二电阻元件的第二端。 正极端子驱动器和负极端子驱动器分别独立地切换以提供具有幅度和方向的电流。 在传输周期期间，每个电阻元件具有与其它电阻元件不同的幅度和/或方向的电流。

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