公开(公告)号：US10169262B2

公开(公告)日：2019-01-01

申请号：US15204755

申请日：2016-07-07

Applicant: QUALCOMM Incorporated

Inventor： David West ,  Vaishnav Srinivas ,  Michael Brunolli ,  Jungwon Suh

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/40 ,  G11C7/22 ,  H03L7/08

Abstract: Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command clock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.

公开(公告)号：US09910482B2

公开(公告)日：2018-03-06

申请号：US14863890

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Michael Brunolli ,  Stephen Thilenius ,  Patrick Isakanian ,  Vaishnav Srinivas

IPC: G06F1/32 ,  G11C7/10 ,  G11C11/4074 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  H04L25/02

CPC classification number: G06F1/3275 ,  G06F1/32 ,  G06F1/3209 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/16 ,  G06F13/4086 ,  G06F13/4243 ,  G11C7/1072 ,  G11C11/4074 ,  H04L25/0278 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.

公开(公告)号：US20170278554A1

公开(公告)日：2017-09-28

申请号：US15622772

申请日：2017-06-14

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  David Ian West

IPC: G11C7/10 ,  G11C29/02

CPC classification number: G11C7/1072 ,  G11C29/022 ,  G11C29/028

Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The signal is then returned to the SoC, where it may be examined by a closed-loop engine of the SoC. A result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

公开(公告)号：US09767868B2

公开(公告)日：2017-09-19

申请号：US14589145

申请日：2015-01-05

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  David Ian West

IPC: G11C7/10 ,  G11C29/02

CPC classification number: G11C7/1072 ,  G11C29/022 ,  G11C29/028

Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A training signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The training signal is then returned to the SoC, where it may be examined by a closed-loop training engine of the SoC. A training result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop training engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

公开(公告)号：US09397646B2

公开(公告)日：2016-07-19

申请号：US14489055

申请日：2014-09-17

Applicant: QUALCOMM Incorporated

Inventor： Guneet Singh ,  Yuehchun Claire Cheng ,  Jan Christian Diffenderfer ,  Vaishnav Srinivas ,  Robert Won Chol Kim

IPC: H03K5/13 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/02 ,  H03K5/00

CPC classification number: H03K5/13 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/028 ,  H03K2005/00019

Abstract: Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.

Abstract translation: 本文描述了用于延迟控制的系统和方法。 在一个实施例中，延迟电路包括第一延迟路径和第二延迟路径。 延迟电路还包括多个开关，其中每个开关耦合在第一和第二延迟路径上的不同点之间，并且每个开关被配置为响应于多个选择信号中的相应一个而导通或关断。 延迟电路还包括多路复用器，其具有耦合到第一延迟路径的输出的第一输入，耦合到第二延迟路径的输出的第二输入和耦合到延迟电路的输出的输出，其中多路复用器 被配置为响应于第二选择信号选择性地将第一和第二延迟路径的输出之一耦合到延迟电路的输出。

公开(公告)号：US09312326B2

公开(公告)日：2016-04-12

申请号：US14688807

申请日：2015-04-16

Applicant: QUALCOMM, Incorporated

Inventor： Renatas Jakushokas ,  Vaishnav Srinivas ,  Robert Won Chol Kim

IPC: H01L49/02 ,  H01L23/522 ,  H01L27/08 ,  H01G4/33 ,  H01G4/38 ,  H01G4/002 ,  H01G4/005

CPC classification number: H01L28/60 ,  H01G4/002 ,  H01G4/005 ,  H01G4/33 ,  H01G4/385 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, and a third electrode formed from a third metal layer, wherein second and third electrodes are spaced farther apart than the first and second electrodes. The capacitor structure also comprises a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third metal layers, wherein the second dielectric layer has a larger thickness than the first dielectric layer. The first electrode is coupled to a first power-supply rail, the third electrode is coupled to a second power-supply rail, and the second power-supply rail has a higher power-supply voltage than the first power-supply rail.

Abstract translation: 本文描述了能够提供低电压电容器和高压电容器的电容器结构。 在一个实施例中，电容器结构包括由第一金属层形成的第一电极，由第二金属层形成的第二电极和由第三金属层形成的第三电极，其中第二和第三电极间隔比第 第一和第二电极。 电容器结构还包括在第一和第二电极之间的第一电介质层和在第二和第三金属层之间的第二电介质层，其中第二电介质层具有比第一电介质层更大的厚度。 第一电极耦合到第一电源轨道，第三电极耦合到第二电源轨道，并且第二电源轨道具有比第一电源轨道更高的电源电压。

公开(公告)号：US20150213850A1

公开(公告)日：2015-07-30

申请号：US14599768

申请日：2015-01-19

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  David Ian West

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F13/1678 ,  G06F13/4243 ,  G06F13/4295 ,  Y02D10/14 ,  Y02D10/151

Abstract: Serial data transmission for dynamic random access memory (DRAM) interfaces is disclosed. Instead of the parallel data transmission that gives rise to skew concerns, exemplary aspects of the present disclosure transmit the bits of a word serially over a single lane of the bus. Because the bus is a high speed bus, even though the bits come in one after another (i.e., serially), the time between arrival of the first bit and arrival of the last bit of the word is still relatively short. Likewise, because the bits arrive serially, skew between bits becomes irrelevant. The bits are aggregated within a given amount of time and loaded into the memory array.

Abstract translation: 公开了用于动态随机存取存储器（DRAM）接口的串行数据传输。 代替引起偏斜关系的并行数据传输，本公开的示例性方面在总线的单个通道上串行地传送字的位。 由于总线是高速总线，即使这些位一个接一个地（即，串行地）进入，第一位到达之间的时间和该字的最后一位的到达仍然相对较短。 同样，由于这些位串行到达，所以位之间的偏移变得无关紧要。 这些位在给定的时间内聚合并加载到存储器阵列中。

公开(公告)号：US10224081B2

公开(公告)日：2019-03-05

申请号：US15849463

申请日：2017-12-20

Applicant: QUALCOMM Incorporated

Inventor： David Ian West ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  Vaishnav Srinivas

IPC: G11C7/10 ,  G06F12/00 ,  G11C11/4076 ,  G06F11/10 ,  G11C11/406

Abstract: Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

公开(公告)号：US09947377B2

公开(公告)日：2018-04-17

申请号：US15622772

申请日：2017-06-14

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  David Ian West

IPC: G06F12/02 ,  G11C7/10 ,  G11C29/02

CPC classification number: G11C7/1072 ,  G11C29/022 ,  G11C29/028

Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The signal is then returned to the SoC, where it may be examined by a closed-loop engine of the SoC. A result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

公开(公告)号：US09734890B1

公开(公告)日：2017-08-15

申请号：US15142306

申请日：2016-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Farrukh Aquil ,  Michael Drop ,  Vaishnav Srinivas ,  Philip Clovis

IPC: G11C11/409 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F13/1678 ,  G06F13/1694 ,  G06F13/4282 ,  G11C7/1072 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4096

Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.