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    Bit remapping system
    21.
    发明授权
    Bit remapping system 有权
    位重映射系统

    公开(公告)号：US09378081B2

    公开(公告)日：2016-06-28

    申请号：US14146628

    申请日：2014-01-02

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jung Pill Kim ,  Mosaddiq Saifuddin

    IPC: G11C29/00 ,  G06F11/07 ,  G06F11/10 ,  G06F12/00 ,  G06F13/16

    CPC classification number: G06F11/076 ,  G06F11/1048 ,  G06F11/1076 ,  G06F12/00 ,  G06F13/16 ,  G06F13/1668 ,  G06F2201/88

    Abstract: A method includes storing, at a counter, a first value indicating a count of read operations in which a bit error is detected in data associated with a first address. The method further includes, in response to the first value exceeding a first threshold value, remapping the first address to a second address using a controller that is coupled to a memory array. The first address corresponds to a first element of the memory array. The second address corresponds to a second element that is included at a memory within the controller. Remapping the first address includes, in response to receiving a first read request for data located at the first address, replacing a first value read from the first element with a second value read from the second element.

    Abstract translation: 一种方法包括在计数器处存储指示在与第一地址相关联的数据中检测到位错误的读取操作的计数的第一值。 该方法还包括响应于第一值超过第一阈值，使用耦合到存储器阵列的控制器将第一地址重新映射到第二地址。 第一个地址对应于存储器阵列的第一个元素。 第二地址对应于包括在控制器内的存储器上的第二元件。 响应于接收到位于第一地址的数据的第一读取请求，重映射第一地址包括用从第二元素读取的第二值替换从第一元素读取的第一值。

    Cache structure with parity-protected clean data and ECC-protected dirty data
    22.
    发明授权
    Cache structure with parity-protected clean data and ECC-protected dirty data 有权
    具有奇偶校验保护的清除数据和ECC保护的脏数据的缓存结构

    公开(公告)号：US09250998B2

    公开(公告)日：2016-02-02

    申请号：US14090427

    申请日：2013-11-26

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jungwon Suh

    IPC: G06F11/10 ,  G06F12/00

    CPC classification number: G06F11/1064 ,  G06F12/00

    Abstract: A method includes generating error detection information associated with data to be stored at a cache in response to determining that the data is clean. The method also includes storing the clean data at a first region of the cache. The method further includes generating error correction information associated with data to be stored at the cache in response to determining that the data is dirty. The method also includes storing the dirty data at a second region of the cache.

    Abstract translation: 响应于确定数据是干净的，一种方法包括生成与要存储在高速缓存中的数据相关联的错误检测信息。 该方法还包括将清洁数据存储在高速缓存的第一区域。 响应于确定数据是脏的，该方法还包括生成与要存储在高速缓存中的数据相关联的纠错信息。 该方法还包括将脏数据存储在高速缓存的第二区域。

    System and method to dynamically determine a timing parameter of a memory device
    23.
    发明授权
    System and method to dynamically determine a timing parameter of a memory device 有权
    用于动态地确定存储器件的定时参数的系统和方法

    公开(公告)号：US09224442B2

    公开(公告)日：2015-12-29

    申请号：US13842410

    申请日：2013-03-15

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jungwon Suh

    IPC: G06F12/00 ,  G11C7/22 ,  G06F3/06 ,  G11C11/4076 ,  G06F17/50 ,  G11C29/02 ,  G11C29/50 ,  G11C29/04

    CPC classification number: G11C7/22 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0629 ,  G06F12/00 ,  G06F17/5031 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/50012 ,  G11C2029/0409 ,  G11C2207/2254

    Abstract: A particular method includes receiving, from a processor, a first memory access request at a memory device. The method also includes processing the first memory access request based on a timing parameter of the memory device. The method further includes receiving, from the processor, a second memory access request at the memory device. The method also includes modifying a timing parameter of the memory device based on addresses identified by the first memory access request and the second memory access request to produce a modified timing parameter. The method further includes processing the second memory access request based on the modified timing parameter.

    Abstract translation: 一种特定的方法包括从处理器接收在存储器设备处的第一存储器访问请求。 该方法还包括基于存储器件的定时参数来处理第一存储器访问请求。 该方法还包括从处理器接收在存储器设备处的第二存储器访问请求。 该方法还包括基于由第一存储器访问请求和第二存储器访问请求识别的地址修改存储器件的定时参数以产生修改的定时参数。 该方法还包括基于修改的定时参数来处理第二存储器访问请求。

    BIT REMAPPING SYSTEM
    25.
    发明申请
    BIT REMAPPING SYSTEM 有权
    位重新系统

    公开(公告)号：US20150186198A1

    公开(公告)日：2015-07-02

    申请号：US14146628

    申请日：2014-01-02

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jung Pill Kim ,  Mosaddiq Saifuddin

    IPC: G06F11/07 ,  G06F11/10

    CPC classification number: G06F11/076 ,  G06F11/1048 ,  G06F11/1076 ,  G06F12/00 ,  G06F13/16 ,  G06F13/1668 ,  G06F2201/88

    Abstract: A method includes storing, at a counter, a first value indicating a count of read operations in which a bit error is detected in data associated with a first address. The method further includes, in response to the first value exceeding a first threshold value, remapping the first address to a second address using a controller that is coupled to a memory array. The first address corresponds to a first element of the memory array. The second address corresponds to a second element that is included at a memory within the controller. Remapping the first address includes, in response to receiving a first read request for data located at the first address, replacing a first value read from the first element with a second value read from the second element.

    Abstract translation: 一种方法包括在计数器处存储指示在与第一地址相关联的数据中检测到位错误的读取操作的计数的第一值。 该方法还包括响应于第一值超过第一阈值，使用耦合到存储器阵列的控制器将第一地址重新映射到第二地址。 第一个地址对应于存储器阵列的第一个元素。 第二地址对应于包括在控制器内的存储器上的第二元件。 响应于接收到位于第一地址的数据的第一读取请求，重映射第一地址包括用从第二元素读取的第二值替换从第一元素读取的第一值。

    CRITICAL-WORD-FIRST ORDERING OF CACHE MEMORY FILLS TO ACCELERATE CACHE MEMORY ACCESSES, AND RELATED PROCESSOR-BASED SYSTEMS AND METHODS
    28.
    发明申请
    CRITICAL-WORD-FIRST ORDERING OF CACHE MEMORY FILLS TO ACCELERATE CACHE MEMORY ACCESSES, AND RELATED PROCESSOR-BASED SYSTEMS AND METHODS 审中-公开
    高速缓存存储器文件的加密缓存存储器访问的关键字第一个命令以及相关的处理器系统和方法

    公开(公告)号：US20140258636A1

    公开(公告)日：2014-09-11

    申请号：US13925874

    申请日：2013-06-25

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong

    IPC: G06F12/12

    CPC classification number: G06F12/128 ,  G06F12/0868 ,  G06F12/0893

    Abstract: Critical-word-first reordering of cache fills to accelerate cache memory accesses, and related processor-based systems and methods are disclosed. In this regard in one embodiment, a cache memory is provided. The cache memory comprises a data array comprising a cache line, which comprises a plurality of data entry blocks configured to store a plurality of data entries. The cache memory also comprises cache line ordering logic configured to critical-word-first order the plurality of data entries into the cache line during a cache fill, and to store a cache line ordering index that is associated with the cache line and that indicates the critical-word-first ordering of the plurality of data entries in the cache line. The cache memory also comprises cache access logic configured to access each of the plurality of data entries in the cache line based on the cache line ordering index for the cache line.

    Abstract translation: 公开了缓存填充的关键字首先重排序以加速缓存存储器访问，以及相关的基于处理器的系统和方法。 在这方面，在一个实施例中，提供了高速缓冲存储器。 高速缓冲存储器包括包括高速缓存线的数据阵列，其包括被配置为存储多个数据条目的多个数据输入块。 高速缓冲存储器还包括高速缓存行排序逻辑，其被配置为在高速缓冲存储器填充期间将多个数据条目重新排序到高速缓存行中，并且存储与高速缓存行相关联的高速缓存行排序索引，并且指示 高速缓存行中的多个数据条目的关键字首先排序。 高速缓冲存储器还包括缓存访问逻辑，其配置为基于高速缓存行的高速缓存行排序索引来访问高速缓存行中的多个数据条目中的每一个。

    DRAM sub-array level autonomic refresh memory controller optimization
    30.
    发明授权
    DRAM sub-array level autonomic refresh memory controller optimization 有权
    DRAM子阵列级自动刷新内存控制器优化

    公开(公告)号：US09524771B2

    公开(公告)日：2016-12-20

    申请号：US14148515

    申请日：2014-01-06

    Applicant: QUALCOMM Incorporated

    Inventor： Deepti Vijayalakshmi Sriramagiri ,  Jungwon Suh ,  Xiangyu Dong

    IPC: G11C11/406 ,  G06F13/16

    CPC classification number: G11C11/40618 ,  G06F13/1636 ,  G11C11/40603 ,  G11C11/40611

    Abstract: A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the DRAM bank when the target refresh row of the DRAM bank is within the open sub-array of the DRAM bank.

    Abstract translation: 一种刷新动态随机存取存储器（DRAM）的方法包括：检测在DRAM存储体的开放子阵列内的DRAM存储体的行的DRAM的打开页面。 该方法还包括当DRAM存储体的目标刷新行位于DRAM存储体的打开子阵列内时，向DRAM存储体的目标刷新行延迟发出刷新命令。

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