公开(公告)号：US20180090475A1

公开(公告)日：2018-03-29

申请号：US15275068

申请日：2016-09-23

Applicant: QUALCOMM Incorporated

Inventor： Chengjie ZUO ,  Jonghae KIM ,  David Francis BERDY ,  Changhan Hobie YUN ,  Niranjan Sunil MUDAKATTE ,  Mario Francisco VELEZ ,  Shiqun GU

IPC: H01L27/01 ,  H01L23/31 ,  H01L23/552 ,  H01L23/528 ,  H01L23/498 ,  H01L21/768 ,  H01L21/56 ,  H01L23/522 ,  H03H7/01 ,  H03H7/46 ,  H04B1/00

CPC classification number: H01L27/01 ,  H01L21/56 ,  H01L21/76885 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49805 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/1815 ,  H01L2924/19011 ,  H01L2924/3025 ,  H03H7/0115 ,  H03H7/468 ,  H04B1/0057 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated circuit (IC) device includes a die having an integrated passive device (IPD) layer. The integrated circuit device also includes a substrate supporting the die, a molding compound surrounding the die. The integrated circuit device further includes a backside conductive layer on a surface of the die that is distal from the IPD layer. The integrated circuit device also includes vias coupling the backside conductive layer to a ground plane through the molding compound.

公开(公告)号：US20180077803A1

公开(公告)日：2018-03-15

申请号：US15261838

申请日：2016-09-09

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  David Francis BERDY ,  Chengjie ZUO ,  Jonghae KIM ,  Niranjan Sunil MUDAKATTE ,  Mario Francisco VELEZ ,  Shiqun GU

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K3/00 ,  H05K3/30 ,  H05K3/40

CPC classification number: H05K1/185 ,  H01G4/224 ,  H01G4/236 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/52 ,  H05K1/162 ,  H05K3/4602 ,  H05K3/4682 ,  H05K3/4688

Abstract: Due to the presence of a glass substrate, it is difficult to fabricate thin conventional passive-on-glass (POG) devices. Also glass dicing has been a throughput bottleneck in fabricating the conventional POG device. To address such disadvantages, devices without the glass substrates are proposed. Support structures may be provided to provide mechanical support. The devices are significantly thinner and allow access to the passive components from both first and second surfaces, which are opposite and exposed surfaces. The proposed POM devices may also be incorporated in a package substrate.

公开(公告)号：US20160126173A1

公开(公告)日：2016-05-05

申请号：US14693820

申请日：2015-04-22

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook KIM ,  Hong Bok WE ,  Jae Sik LEE ,  Shiqun GU

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/09 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/08238 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/83005 ,  H01L2924/01073 ,  H01L2924/15311 ,  H01L2924/15321

Abstract: A high density fan out package structure may include a contact layer. The contact layer includes a conductive interconnect layer having a first surface facing an active die and a second surface facing a redistribution layer. The high density fan out package structure has a barrier layer on the first surface of the conductive interconnect layer. The high density fan out package structure may also include the redistribution layer, which has conductive routing layers. The conductive routing layers may be configured to couple a first conductive interconnect to the conductive interconnect layer. The high density fan out package structure may further include a first via coupled to the barrier liner and configured to couple with a second conductive interconnect to the active die.

Abstract translation: 高密度扇形封装结构可包括接触层。 接触层包括导电互连层，其具有面向活性管芯的第一表面和面向再分布层的第二表面。 高密度扇形外壳结构在导电互连层的第一表面上具有阻挡层。 高密度风扇输出封装结构还可以包括具有导电布线层的再分配层。 导电路由层可以被配置为将第一导电互连件耦合到导电互连层。 高密度扇出器封装结构还可以包括耦合到阻挡衬里并被配置为将第二导电互连件耦合到有源裸片的第一通孔。

公开(公告)号：US20150249209A1

公开(公告)日：2015-09-03

申请号：US14195566

申请日：2014-03-03

Applicant: QUALCOMM Incorporated

Inventor： Yu LU ,  Xia LI ,  Seung Hyuk KANG ,  Shiqun GU

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L21/76802 ,  H01L21/76813 ,  H01L21/76832 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: Systems and methods for forming precise and self-aligned top metal contact for a Magnetoresistive random-access memory (MRAM) device include forming a magnetic tunnel junction (MTJ) in a common interlayer metal dielectric (IMD) layer with a logic element. A low dielectric constant (K) etch stop layer is selectively retained over an exposed top surface of the MTJ. Etching is selectively performed through a top IMD layer formed over the low K etch stop layer and the common IMD layer, based on a first chemistry which prevents etching through the low K etch stop layer. By switching chemistry to a second chemistry which precisely etches through the low K etch stop layer, an opening is created for forming a self-aligned top contact to the exposed top surface of the MTJ.

Abstract translation: 用于形成用于磁阻随机存取存储器（MRAM）器件的精确和自对准的顶部金属接触的系统和方法包括在具有逻辑元件的公共层间金属电介质（IMD）层中形成磁性隧道结（MTJ）。 低介电常数（K）蚀刻停止层选择性地保留在MTJ的暴露的顶表面上。 基于防止蚀刻通过低K蚀刻停止层的第一化学反应，通过形成在低K蚀刻停止层和公共IMD层上的顶部IMD层选择性地进行蚀刻。 通过将化学转换成精确地蚀刻通过低K蚀刻停止层的第二化学物质，形成一个开口以形成与MTJ暴露的顶表面的自对准顶部接触。