公开(公告)号：US20160293574A1

公开(公告)日：2016-10-06

申请号：US15043484

申请日：2016-02-12

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook KIM ,  Hong Bok WE ,  Jae Sik LEE ,  Shiqun GU

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1146 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14151 ,  H01L2224/14155 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1624 ,  H01L2224/171 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/49173 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/92 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/81 ,  H01L21/76898

Abstract: Some examples of the disclosure may include a package on package integrated package configuration including a first die located above the substrate in a first plane, a second die located above the first die in a second plane with a portion extending past the first die, a third die located above the first die in the second plane with a portion extending past the first die, a fourth die located above the second die and the third die in a third plane with a portion extending past the second die and the third die, and a fifth die located above the second die and the third die in the third plane with a portion extending past the second die and the third die.

Abstract translation: 本公开的一些示例可以包括封装集成封装结构，其包括位于第一平面中的衬底上方的第一管芯，在第二平面中位于第一管芯上方的第二管芯，其中延伸超过第一管芯的部分， 在所述第二平面中位于所述第一模具的上方，具有延伸经过所述第一模具的部分，位于所述第二模具上方的第四模具和位于延伸通过所述第二模具和所述第三模具的部分的第三平面中的所述第三模具， 第五模具位于第二模具的上方，第三模具在第三平面中具有延伸经过第二模具和第三模具的部分。

公开(公告)号：US20160172344A1

公开(公告)日：2016-06-16

申请号：US14572753

申请日：2014-12-16

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Dong Wook KIM ,  Kyu-Pyung HWANG ,  Young Kyu SONG

IPC: H01L25/10 ,  H01L23/04 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/13 ,  H01L23/142 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24247 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15155 ,  H01L2924/15311 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/3511

Abstract: The present disclosure provides semiconductor packages and methods for fabricating PoP semiconductor packages. The PoP semiconductor package may comprise a first semiconductor package, the first semiconductor package comprising an anodized metal lid structure comprising (i) a central cavity having a central cavity opening direction and (ii) at least one perimeter cavity having a perimeter cavity opening direction facing in an opposite direction of the central cavity opening direction, a first semiconductor device arranged in the central cavity of the anodized metal lid structure, a redistribution layer electrically coupled to the first semiconductor device, wherein a conductive trace formed in the redistribution layer is exposed to the at least one perimeter cavity, and solder material arranged in the at least one perimeter cavity, and a second semiconductor package, the second semiconductor package comprising at least one conductive post, wherein the at least one conductive post is electrically coupled to the solder material arranged in the at least one perimeter cavity.

Abstract translation: 本公开提供了用于制造PoP半导体封装的半导体封装和方法。 PoP半导体封装可以包括第一半导体封装，第一半导体封装包括阳极氧化的金属盖结构，其包括（i）具有中心腔打开方向的中心空腔和（ii）至少一个周边空腔，其具有面向 在与中心腔打开方向相反的方向上，布置在阳极化金属盖结构的中心空腔中的第一半导体器件，电耦合到第一半导体器件的再分配层，其中形成在再分配层中的导电迹线暴露于 所述至少一个周边空腔和布置在所述至少一个周边空腔中的焊料材料以及第二半导体封装，所述第二半导体封装包括至少一个导电柱，其中所述至少一个导电柱电耦合到所述焊料材料 布置在所述至少一个周边空腔中。

公开(公告)号：US20160093571A1

公开(公告)日：2016-03-31

申请号：US14498076

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook KIM ,  Jae Sik LEE ,  Hong Bok WE ,  Young Kyu SONG ,  Chin-Kwan KIM ,  Kyu-Pyung HWANG ,  Shiqun GU

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: A semiconductor package according to some examples of the disclosure may include a base with a first redistribution layer on one side, first and second side by side die attached to the base on an opposite side from the first redistribution layer, an interposer attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias extending from the first and second die to a second redistribution layer on a surface of the package opposite the first redistribution layer, and a plurality of package vias extending through the package between the first and second redistribution layers.

Abstract translation: 根据本公开的一些示例的半导体封装可以包括在一侧具有第一再分布层的基底，在与第一再分布层相反的一侧上附接到基部的第一和第二并排裸片，附接到主动侧的插入件 以提供第一和第二管芯之间的互连，从第一和第二管芯延伸到在与第一再分布层相对的封装的表面上的第二再分配层的多个管芯通孔，以及多个 在第一和第二再分配层之间延伸穿过包装的通孔。

公开(公告)号：US20150084623A1

公开(公告)日：2015-03-26

申请号：US14037142

申请日：2013-09-25

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung HWANG ,  Young K. SONG ,  Dong Wook KIM ,  Changhan Hobie YUN

IPC: G01R33/02

CPC classification number: G01R33/02 ,  G01R29/0814

Abstract: A method and apparatus for testing near field magnetic fields of electronic devices. The method comprises measuring a magnetic field using a loop antenna that is oriented in a first direction. The loop antenna is swept through a desired range of azimuth angles while measuring the magnetic field. Once the first direction testing is completed, the loop antenna is changed to a second orientation direction. The magnetic field is then measured in the second orientation direction and is swept through a desired range of orientation angles in the second direction. The apparatus provides a loop antenna connected to a coaxial probe, with the coaxial cable serving as the center conductor, and two outer conductors. An axle is mounted to the loop antenna and connected to a step motor. A servo motor is also provided for moving the arm assembly.

Abstract translation: 一种用于测试电子设备的近场磁场的方法和装置。 该方法包括使用在第一方向上定向的环形天线来测量磁场。 在测量磁场的同时，将环形天线扫过所需的方位角范围。 一旦第一方向测试完成，环形天线就变成第二定位方向。 然后在第二取向方向上测量磁场，并且扫过第二方向上所需的取向角范围。 该装置提供连接到同轴探针的环形天线，同轴电缆用作中心导体和两个外部导体。 轴安装在环形天线上，并连接到步进电机。 还提供用于移动臂组件的伺服电动机。

公开(公告)号：US20160329284A1

公开(公告)日：2016-11-10

申请号：US14844185

申请日：2015-09-03

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Dong Wook KIM ,  Jae Sik LEE

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L21/768 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/3157 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/19 ,  H01L24/25 ,  H01L24/27 ,  H01L24/33 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/19 ,  H01L2224/2205 ,  H01L2224/221 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: A semiconductor package according to some examples of the disclosure may include a substrate having a bridge embedded in the substrate, a first and second die coupled to the substrate, and a plurality of electrically conductive bridge interconnects in the substrate coupling the bridge to the first and second die. The plurality of electrically conductive bridge interconnects may have a first bridge contact layer directly coupled to the bridge, a first solder layer on the first bridge contact layer, a second bridge contact layer on the first solder layer, a second solder layer on the second bridge contact layer, and a die contact directly coupled to one of the first and second die where the plurality of electrically conductive bridge interconnects are embedded in the substrate.

Abstract translation: 根据本公开的一些示例的半导体封装可以包括具有嵌入在衬底中的桥的衬底，耦合到衬底的第一和第二裸片以及耦合到第一和第二衬底的衬底中的多个导电桥互连 第二次死亡 多个导电桥互连可以具有直接耦合到桥的第一桥接触层，第一桥接触层上的第一焊料层，第一焊料层上的第二桥接触层，第二桥上的第二焊料层 接触层和直接耦合到所述第一和第二管芯中的一个的管芯接触，其中所述多个导电桥互连件嵌入在所述衬底中。

公开(公告)号：US20160218082A1

公开(公告)日：2016-07-28

申请号：US14689011

申请日：2015-04-16

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik LEE ,  Hong Bok WE ,  Dong Wook KIM

IPC: H01L25/065 ,  H01L23/522 ,  H01L25/00 ,  H01L21/768 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2924/0002 ,  H01L2924/18162 ,  H01L2924/00

Abstract: A semiconductor device may include a first semiconductor die. A passivation layer supports the first semiconductor die. The passivation layer may include a first via having a barrier layer and a first redistribution layer (RDL) conductive interconnect coupled to the first via through the barrier layer. The first via may couple the first semiconductor die to the first RDL conductive interconnect.

Abstract translation: 半导体器件可以包括第一半导体管芯。 钝化层支撑第一半导体管芯。 钝化层可以包括具有阻挡层的第一通孔和通过阻挡层耦合到第一通孔的第一再分布层（RDL）导电互连。 第一通孔可以将第一半导体管芯耦合到第一RDL导电互连。

公开(公告)号：US20150091132A1

公开(公告)日：2015-04-02

申请号：US14042140

申请日：2013-09-30

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook KIM ,  Kyu-Pyung HWANG ,  Young Kyu SONG ,  Changhan Hobie YUN

IPC: H01L21/52 ,  H01L23/04 ,  H01L21/48 ,  H01L49/02 ,  H01L23/13

CPC classification number: H01L21/52 ,  H01L21/4817 ,  H01L23/04 ,  H01L23/13 ,  H01L23/16 ,  H01L28/60 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Systems and methods for preventing warpage of a semiconductor substrate in a semiconductor package. A continuous or uninterrupted stiffener structure is designed with a recessed groove, such that passive components, such as, high density capacitors are housed within the recessed groove. The stiffener structure with the recessed groove is attached to the semiconductor substrate using anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). The stiffener structure with the recessed groove surrounds one or more semiconductor devices that may be formed on the semiconductor substrate. The stiffener structure with the recessed groove does not extend beyond horizontal boundaries of the semiconductor substrate.

Abstract translation: 用于防止半导体封装中的半导体衬底翘曲的系统和方法。 连续或不间断的加强结构设计有凹槽，使得诸如高密度电容器的无源部件容纳在凹槽内。 具有凹槽的加强结构使用各向异性导电膜（ACF）或各向异性导电膏（ACP）附着到半导体衬底上。 具有凹槽的加强结构围绕可形成在半导体衬底上的一个或多个半导体器件。 具有凹槽的加强结构不延伸超过半导体衬底的水平边界。

公开(公告)号：US20160293572A1

公开(公告)日：2016-10-06

申请号：US14673435

申请日：2015-03-30

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Jae Sik LEE ,  Dong Wook KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32137 ,  H01L2224/81192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/381 ,  H01L2924/00014

Abstract: An integrated circuit (IC) package structure may include a substrate. The substrate may include a semiconductor bridge having a first surface directly on a surface of the substrate that faces a first semiconductor die and a second semiconductor die. The semiconductor bridge may be disposed within a cavity extending through a photo-sensitive layer on the surface of the substrate. The semiconductor bridge may have an exposed, second surface substantially flush with the photo-sensitive layer. The first semiconductor die and the second semiconductor die are supported by the substrate and coupled together through the semiconductor bridge.

Abstract translation: 集成电路（IC）封装结构可以包括衬底。 衬底可以包括半导体电桥，其具有直接位于衬底的面向第一半导体管芯和第二半导体管芯的表面上的第一表面。 半导体桥可以设置在延伸穿过衬底表面上的光敏层的空腔内。 半导体桥可以具有基本上与光敏层齐平的暴露的第二表面。 第一半导体管芯和第二半导体管芯由衬底支撑并通过半导体桥耦合在一起。

公开(公告)号：US20160126173A1

公开(公告)日：2016-05-05

申请号：US14693820

申请日：2015-04-22

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook KIM ,  Hong Bok WE ,  Jae Sik LEE ,  Shiqun GU

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/09 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/08238 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/83005 ,  H01L2924/01073 ,  H01L2924/15311 ,  H01L2924/15321

Abstract: A high density fan out package structure may include a contact layer. The contact layer includes a conductive interconnect layer having a first surface facing an active die and a second surface facing a redistribution layer. The high density fan out package structure has a barrier layer on the first surface of the conductive interconnect layer. The high density fan out package structure may also include the redistribution layer, which has conductive routing layers. The conductive routing layers may be configured to couple a first conductive interconnect to the conductive interconnect layer. The high density fan out package structure may further include a first via coupled to the barrier liner and configured to couple with a second conductive interconnect to the active die.

Abstract translation: 高密度扇形封装结构可包括接触层。 接触层包括导电互连层，其具有面向活性管芯的第一表面和面向再分布层的第二表面。 高密度扇形外壳结构在导电互连层的第一表面上具有阻挡层。 高密度风扇输出封装结构还可以包括具有导电布线层的再分配层。 导电路由层可以被配置为将第一导电互连件耦合到导电互连层。 高密度扇出器封装结构还可以包括耦合到阻挡衬里并被配置为将第二导电互连件耦合到有源裸片的第一通孔。

公开(公告)号：US20160035664A1

公开(公告)日：2016-02-04

申请号：US14450201

申请日：2014-08-01

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Dong Wook KIM ,  Jae Sik LEE ,  Kyu-Pyung HWANG ,  Young Kyu SONG

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L25/11

CPC classification number: H01L23/49861 ,  H01L21/4853 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A package on package structure may be formed by fabricating or providing a bottom package having a substrate, at least one die on top of the substrate, and bonding pads on the top of the substrate. Next, a frame is formed on the bonding pads and connected to the bonding pads. Next, a package material is molded over the top of the substrate to encapsulate the frame, the die, and the pads or substantially encapsulates these components. Next, a portion of the molded package material is removed to expose at least a portion of the frame. The exposed frame portions are formed such that a desired fan in or fan out configuration is obtained. Next, a non-conductive layer is formed on the exposed frame. Last, a second package having a die or chip is connected to the exposed portion of the frame to form a package on package structure.

Abstract translation: 可以通过制造或提供具有衬底的底部封装，在衬底顶部上的至少一个管芯和衬底顶部上的焊盘来形成封装结构。 接下来，在接合焊盘上形成框架并连接到接合焊盘。 接下来，在衬底的顶部上模制封装材料以封装框架，模具和衬垫，或者基本上封装这些部件。 接下来，去除模制包装材料的一部分以暴露框架的至少一部分。 形成暴露的框架部分，使得获得所需的风扇或扇出配置。 接下来，在暴露的框架上形成非导电层。 最后，具有芯片或芯片的第二封装连接到框架的暴露部分以形成封装结构上的封装。