公开(公告)号：US20080048169A1

公开(公告)日：2008-02-28

申请号：US11467294

申请日：2006-08-25

申请人： James P. Doyle ,  Bruce G. Elmegreen ,  Lia Krusin-Elbaum ,  Chung Hon Lam ,  Xiao Hu Liu ,  Dennis M. Newns ,  Christy S. Tyberg

发明人： James P. Doyle ,  Bruce G. Elmegreen ,  Lia Krusin-Elbaum ,  Chung Hon Lam ,  Xiao Hu Liu ,  Dennis M. Newns ,  Christy S. Tyberg

IPC分类号： H01L47/00 ,  H01L21/76

CPC分类号： H01L45/1233 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.

摘要翻译： 用于集成电路器件的电可重新编程保险丝（eFUSE）器件包括细长的加热器元件，围绕细长加热器元件的外表面的电绝缘衬垫，其对应于其纵向轴线，留下细长加热器的相对端 元件与第一和第二加热器电极电接触。 相变材料（PCM）围绕电绝缘衬垫的外表面的一部分，热和电绝缘层围绕PCM的外表面，其中第一和第二熔丝电极与PCM的相对端电接触。 PCM被封装在电绝缘衬垫，热和电绝缘层以及第一和第二熔丝电极中。

公开(公告)号：US07329600B2

公开(公告)日：2008-02-12

申请号：US10817179

申请日：2004-04-02

申请人： Lawrence Clevenger ,  Louis Hsu ,  Christy S. Tyberg ,  Tsorng-Dih Yuan

发明人： Lawrence Clevenger ,  Louis Hsu ,  Christy S. Tyberg ,  Tsorng-Dih Yuan

IPC分类号： H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for fabricating a low dielectric constant semiconductor comprising the steps of: depositing a first metal layer on a substrate; patterning the first metal layer to produce a patterned first metal wiring; applying a first insulating material onto the patterned first metal wiring to form a support structure; patterning the first insulating material by a contact printing process; depositing a second insulating material of lower dielectric constant onto the support structure; planarizing the second insulating material; depositing a polish-stop film layer over the planarized second insulating material, thereby forming a plurality of metal studs; depositing a second metal layer onto the polish-stop film layer forming interconnects with said studs; and patterning the metal layer to produce a second metal wiring interconnecting to the first wiring via the metal studs.

摘要翻译： 一种制造低介电常数半导体的方法，包括以下步骤：在衬底上沉积第一金属层; 图案化第一金属层以产生图案化的第一金属布线; 将第一绝缘材料施加到所述图案化的第一金属布线上以形成支撑结构; 通过接触印刷方法图案化第一绝缘材料; 将较低介电常数的第二绝缘材料沉积到所述支撑结构上; 平面化第二绝缘材料; 在平坦化的第二绝缘材料上沉积抛光停止膜层，从而形成多个金属螺柱; 将第二金属层沉积到所述抛光 - 停止膜层上，形成与所述螺柱的互连; 以及图案化所述金属层以产生经由所述金属螺柱与所述第一布线互连的第二金属布线。

公开(公告)号：US06638878B2

公开(公告)日：2003-10-28

申请号：US09969361

申请日：2001-10-02

申请人： Darryl D. Restaino ,  Jeffrey C. Hedrick ,  John A. Fitzsimmons ,  Christy S. Tyberg ,  Chih-Chien Liu ,  Shahab Siddiqui

发明人： Darryl D. Restaino ,  Jeffrey C. Hedrick ,  John A. Fitzsimmons ,  Christy S. Tyberg ,  Chih-Chien Liu ,  Shahab Siddiqui

IPC分类号： H01L21461

CPC分类号： H01L21/02304 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/31051 ,  H01L21/31058 ,  H01L21/312 ,  Y10T428/29 ,  Y10T428/31504

摘要： A method for forming a planarized dielectric layer upon a semiconductor wafer is disclosed. In an exemplary embodiment of the invention, the method includes applying an adhesion promoter to the wafer, thereby forming an adhesion promoter layer. A dielectric material is applied in a spin-on fashion upon the adhesion promoter layer at a relative humidity of less than 40% and for a thickness setting duration of less than 30 seconds. Then, the dielectric material is dried by baking without additional spinning of the semiconductor wafer.

摘要翻译： 公开了一种在半导体晶片上形成平坦化电介质层的方法。 在本发明的一个示例性实施方案中，该方法包括将粘合促进剂施加到晶片上，从而形成粘附促进剂层。 将介电材料以相对湿度小于40％并且厚度设定持续时间小于30秒以旋涂方式施加到粘合促进剂层上。 然后，通过烘烤干燥电介质材料，而不需要半导体晶片的额外纺丝。

公开(公告)号：US08569803B2

公开(公告)日：2013-10-29

申请号：US13572742

申请日：2012-08-13

申请人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

发明人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

IPC分类号： H01L29/76

CPC分类号： H01L23/5226 ,  H01L23/53271 ,  H01L27/124 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

摘要翻译： 本发明提供了用于在线路后端（BEOL）互连结构中并入薄膜晶体管的结构和制造工艺。 所描述的结构和制造工艺与BEOL互连结构的处理要求相兼容。 结构和制造工艺利用已经并入到互连布线层中的现有处理步骤和材料，以便降低与在这些层级中引入薄膜晶体管相关联的附加成本。 与现有技术的3D集成方法相比，该结构能够实现多层次的垂直（3D）集成，具有改进的可制造性和可靠性。

公开(公告)号：US07879717B2

公开(公告)日：2011-02-01

申请号：US12140854

申请日：2008-06-17

申请人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

发明人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

IPC分类号： H01L21/00

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括由具有组成SivNwCxOyHz的聚合物材料构成的掩埋蚀刻停止层，其中0.05和n1E; v和n1E; 0.8,0和n1E; w和n1E;0.9,0.05≤n1E; x和nlE; 0.8,0和nlE; y＆nlE; 0.3,0.05＆ 对于v + w + x + y + z = 1，z＆nlE; 0.8。 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。

公开(公告)号：US07187081B2

公开(公告)日：2007-03-06

申请号：US10699238

申请日：2003-10-31

申请人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

发明人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

IPC分类号： H01L29/40

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括掩埋的蚀刻停止层，其由具有下列成分的聚合物材料构成：其中X 1，X，Y， 其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8,0 <= y <= 0.3,0.05 对于v + w + x + y + z = 1，z <= 0.8; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。

公开(公告)号：US06982227B2

公开(公告)日：2006-01-03

申请号：US10687294

申请日：2003-10-16

申请人： Edward C. Cooney, III ,  Robert M. Geffken ,  Vincent J. McGahay ,  William T. Motsiff ,  Mark P. Murray ,  Amanda L. Piper ,  Anthony K. Stamper ,  David C. Thomas ,  Christy S. Tyberg ,  Elizabeth T. Webster

发明人： Edward C. Cooney, III ,  Robert M. Geffken ,  Vincent J. McGahay ,  William T. Motsiff ,  Mark P. Murray ,  Amanda L. Piper ,  Anthony K. Stamper ,  David C. Thomas ,  Christy S. Tyberg ,  Elizabeth T. Webster

IPC分类号： H01L21/302

CPC分类号： H01L21/76808 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76892 ,  H01L23/525 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.

摘要翻译： 一种重新加工BEOL（处理线的后端）金刚石冶金的金​​属化水平的方法包括在衬底上形成多个BEOL金属化水平，在BEOL金属化水平中形成线和通孔部分，选择性地去除BEOL金属化中的至少一个 以暴露线路和通孔部分，并且用至少一个新的BEOL金属化水平替换去除的BEOL金属化水平，其中BEOL金属化水平包括第一介电层和第二介电层，并且其中第一介电层包括下部 介电常数材料比第二介电层。

公开(公告)号：US06818285B2

公开(公告)日：2004-11-16

申请号：US10334413

申请日：2002-12-31

申请人： Jeffrey C. Hedrick ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg ,  James P. Godschalx ,  Qingshan J. Niu ,  Harry C. Silvis

发明人： Jeffrey C. Hedrick ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg ,  James P. Godschalx ,  Qingshan J. Niu ,  Harry C. Silvis

IPC分类号： B32B310

CPC分类号： H01L23/5329 ,  C08G61/00 ,  C08G61/10 ,  C08G2261/312 ,  C08G2261/46 ,  C08G2261/92 ,  C08G2650/20 ,  C08G2650/60 ,  C08L65/00 ,  C08L2203/20 ,  C08L2312/00 ,  C09D165/00 ,  H01L2924/0002 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/31504 ,  Y10T428/31855 ,  H01L2924/00

摘要： A crosslinked polyarylene material with a reduced coefficient of thermal expansion at high temperatures compared with conventional crosslinked polyarylene materials is provided. In addition, an integrated circuit article containing a crosslinked polyarylene polymer with reduced coefficient of thermal expansion at high temperatures is provided.

公开(公告)号：US08278155B2

公开(公告)日：2012-10-02

申请号：US13100456

申请日：2011-05-04

申请人： Geoffrey W. Burr ,  Chandrasekharan Kothandaraman ,  Chung Hon Lam ,  Xiao Hu Liu ,  Stephen M. Rossnagel ,  Christy S. Tyberg ,  Robert L. Wisnieff

发明人： Geoffrey W. Burr ,  Chandrasekharan Kothandaraman ,  Chung Hon Lam ,  Xiao Hu Liu ,  Stephen M. Rossnagel ,  Christy S. Tyberg ,  Robert L. Wisnieff

IPC分类号： H01L21/82 ,  H01L21/326 ,  H01L21/479

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.

摘要翻译： 集成电路中的可逆熔丝结构通过实现具有短路相变材料的熔断电池获得，所述相变材料与能够使电流通过相变材料线（熔丝电池）的通孔和线结构相接触。 电流通过熔丝电池，以便通过将结晶状态的相变材料加热至熔点，从而将材料从较小电阻的材料转变为更电阻的材料，然后快速将材料淬火成非晶状态。 可逆编程通过使较低电流通过熔丝电池来实现，以将高电阻率无定形材料转换成较低电阻率的晶体材料。 集成适当的感测电路以读取存储在熔丝中的信息，其中所述感测电路用于启用或禁用电路。

公开(公告)号：US07755921B2

公开(公告)日：2010-07-13

申请号：US11838663

申请日：2007-08-14

申请人： Solomon Assefa ,  Michael C. Gaidis ,  Eric A. Joseph ,  Stuart Stephen Papworth Parkin ,  Christy S. Tyberg

发明人： Solomon Assefa ,  Michael C. Gaidis ,  Eric A. Joseph ,  Stuart Stephen Papworth Parkin ,  Christy S. Tyberg

IPC分类号： G11C19/00

CPC分类号： H01L27/222 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C19/0808 ,  H01L21/76816 ,  H01L43/08

摘要： In one embodiment, the invention is a method and apparatus for fabricating sub-lithography data tracks for use in magnetic shift register memory devices. One embodiment of a memory device includes a first stack of dielectric material formed of a first dielectric material, a second stack of dielectric material surrounding the first stack of dielectric material and formed of at least a second dielectric material, and at least one data track for storing information, positioned between the first stack of dielectric material and the second stack of dielectric material, the data track having a high aspect ratio and a substantially rectangular cross section.

摘要翻译： 在一个实施例中，本发明是用于制造用于磁移位寄存器存储器件的子光刻数据磁道的方法和装置。 存储器件的一个实施例包括由第一电介质材料形成的介电材料的第一叠层，围绕第一电介质材料堆叠并由至少第二电介质材料形成的第二电介质材料叠层，以及至少一个用于 存储位于所述第一电介质材料堆叠和所述第二电介质材料堆之间的信息，所述数据轨道具有高纵横比和基本上矩形的横截面。