公开(公告)号：US20190019886A1

公开(公告)日：2019-01-17

申请号：US16135298

申请日：2018-09-19

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L21/265 ,  H01L21/266 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L21/02 ,  H01L29/20 ,  H01L29/10 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7787 ,  H01L21/02694 ,  H01L21/2258 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/266 ,  H01L29/0688 ,  H01L29/1066 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7783

Abstract: A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.

公开(公告)号：US20180342589A1

公开(公告)日：2018-11-29

申请号：US15966773

申请日：2018-04-30

Applicant: Renesas Electronics Corporation

Inventor： Hironobu MIYAMOTO ,  Tatsuo NAKAYAWA ,  Yasuhiro OKAMOTO ,  Atsushi TSUBOI

IPC: H01L29/20 ,  H01L29/08 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L29/2003 ,  H01L21/0262 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/432 ,  H01L29/513 ,  H01L29/66462 ,  H01L29/7783

Abstract: Characteristics of a semiconductor device using a nitride semiconductor are improved. A semiconductor device of the present invention includes a buffer layer, a channel layer, a barrier layer, a mesa-type 2DEG dissolving layer, a source electrode, a drain electrode, a gate insulating film formed on the mesa-type 2DEG dissolving layer, and an overlying gate electrode. The gate insulating film of the semiconductor device includes a sputtered film formed on the mesa-type 2DEG dissolving layer and a CVD film formed on the sputtered film. The sputtered film is formed in a non-oxidizing atmosphere by a sputtering process using a target including an insulator. This makes it possible to reduce positive charge amount at a MOS interface and in gate insulating film and increase a threshold voltage, and thus improve normally-off characteristics.

公开(公告)号：US20170005189A1

公开(公告)日：2017-01-05

申请号：US15265328

申请日：2016-09-14

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro OKAMOTO ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L29/205 ,  H01L21/02 ,  H01L29/417 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a third semiconductor layer formed over the second semiconductor layer, a gate electrode formed over the third semiconductor layer, and a gate insulating film formed between the third semiconductor layer and the gate electrode. The second semiconductor layer includes an Alyα1-yN layer (α includes Ga or In, and 0≦y y” at an interface between the second nitride semiconductor layer and the third nitride semiconductor layer.

Abstract translation: 半导体器件包括第一半导体层，形成在第一半导体层上的第二半导体层，形成在第二半导体层上的第三半导体层，形成在第三半导体层上的栅电极和形成在第三半导体层之间的栅极绝缘膜 半导体层和栅电极。 第二半导体层包括Alyα1-yN层（α包括Ga或In，并且0≤y<1），第三半导体层包括Alzα1-zN层（0≤z<1）。 形成第二半导体层的Alyα1-yN层的y至少在栅极下方的区域从第三半导体层增加到第一半导体层。 在第二氮化物半导体层和第三氮化物半导体层之间的界面处存在关系“z> y”。

公开(公告)号：US20160204243A1

公开(公告)日：2016-07-14

申请号：US15079879

申请日：2016-03-24

Applicant: Renesas Electronics Corporation

Inventor： Takashi INOUE ,  Toshiyuki TAKEWAKI ,  Tatsuo NAKAYAMA ,  Yasuhiro OKAMOTO ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L23/31 ,  H01L29/205 ,  H01L23/29 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/518 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.

公开(公告)号：US20160064538A1

公开(公告)日：2016-03-03

申请号：US14837053

申请日：2015-08-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Yasuhiro OKAMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/15 ,  H01L29/66 ,  H01L29/207 ,  H01L29/06 ,  H01L21/02 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

Abstract translation: 改善了半导体器件的特性。 半导体器件具有在衬底上形成的含有ap型杂质，沟道层和阻挡层的电位固定层，以及布置在穿过势垒层的沟槽中的栅极，并且通过沟道层的某一点通过 门绝缘膜。 源极和漏极形成在栅电极的相对侧上。 含p型杂质的电位固定层在栅电极和漏电极之间具有含有诸如氢之类的钝化元件的失活区域。 因此，在提高源电极侧的电位固定层的p型杂质（受体）浓度的同时，在漏电极侧使电位固定层的p型杂质失活。 这可以提高漏极侧击穿电压，同时通过p型杂质提供电荷的去除效果。

公开(公告)号：US20150221758A1

公开(公告)日：2015-08-06

申请号：US14590433

申请日：2015-01-06

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao MIURA ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/205 ,  H01L29/20 ,  H01L29/201

CPC classification number: H01L29/7787 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has, over a substrate thereof, a first buffer layer (GaN), a second buffer layer (AlGaN), a channel layer, and a barrier layer, a trench penetrating through the barrier layer and reaching the middle of the channel layer, a gate electrode placed in the trench via a gate insulating film, and a source electrode and a drain electrode formed on both sides of the gate electrode respectively. By a coupling portion in a through-hole reaching the first buffer layer, the buffer layer and the source electrode are electrically coupled to each other. Due to a two-dimensional electron gas produced in the vicinity of the interface between these two buffer layers, the semiconductor device can have an increased threshold voltage and improved normally-off characteristics.

Abstract translation: 提供具有改进特性的半导体器件。 半导体器件在其衬底上具有第一缓冲层（GaN），第二缓冲层（AlGaN），沟道层和势垒层，穿过阻挡层并到达沟道层中间的沟槽 通过栅极绝缘膜放置在沟槽中的栅电极，以及分别形成在栅极两侧的源电极和漏电极。 通过到达第一缓冲层的通孔中的耦合部分，缓冲层和源电极彼此电耦合。 由于在这两个缓冲层之间的界面附近产生的二维电子气，所以半导体器件可以具有增加的阈值电压和改善的常关特性。

公开(公告)号：US20140015019A1

公开(公告)日：2014-01-16

申请号：US13937846

申请日：2013-07-09

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro OKAMOTO ,  Takashi INOUE ,  Tatsuo NAKAYAMA ,  Ryohei NEGA ,  Masaaki KANAZAWA ,  Hironobu MIYAMOTO

IPC: H01L29/78

CPC classification number: H01L29/452 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.

Abstract translation: 提高了由氮化物半导体材料制成的场效应晶体管的可靠性。 欧姆电极包括被隔离以彼此分离的多个单元电极。 由此，能够防止在y轴方向（负方向）在单位电极中流通导通电流。 此外，在各单元电极中，可以防止沿y轴方向（负方向）流动的通态电流的电流密度增加。 结果，可以提高欧姆电极的电迁移电阻。

公开(公告)号：US20210184054A1

公开(公告)日：2021-06-17

申请号：US16951692

申请日：2020-11-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hironobu MIYAMOTO ,  Masami SAWADA ,  Tatsuya USAMI ,  Tomoo NAKAYAMA

IPC: H01L29/861 ,  H01L29/24 ,  H01L29/66

Abstract: A gallium oxide diode includes: a gallium oxide substrate having an n-type gallium oxide drift layer; an anode electrode of a metal film formed over a front surface of the n-type gallium oxide drift layer; a cathode electrode formed over a rear surface of the gallium oxide substrate; and a reaction layer of a metal oxide film of p-type conductivity formed between the anode electrode and the n-type gallium oxide drift layer. Further, a manufacturing method of a gallium oxide diode includes steps of forming an anode electrode of a metal film over an n-type gallium oxide drift layer formed over a gallium oxide substrate; and forming a reaction layer between the anode electrode and the n-type gallium oxide drift layer by performing a heat treatment to the gallium oxide substrate after forming the anode electrode, the reaction layer being made of a metal oxide film with p-type conductivity.

公开(公告)号：US20180061983A1

公开(公告)日：2018-03-01

申请号：US15789191

申请日：2017-10-20

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Yasuhiro OKAMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

公开(公告)号：US20170294538A1

公开(公告)日：2017-10-12

申请号：US15632663

申请日：2017-06-26

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Yasuhiro OKAMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.