公开(公告)号：US20130265109A1

公开(公告)日：2013-10-10

申请号：US13904788

申请日：2013-05-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya IIDA ,  Akihiko FURUKAWA ,  Satoshi YAMAKAWA ,  Tsuyoshi KAWAKAMI ,  Masao KONDO ,  Yutaka HOSHINO

IPC: H03F3/21

CPC classification number: H03F3/211 ,  H03F1/56 ,  H03F3/26 ,  H03F2200/537 ,  H03F2203/21139

Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.

公开(公告)号：US20130207228A1

公开(公告)日：2013-08-15

申请号：US13748873

申请日：2013-01-24

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya IIDA

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L29/7824 ,  H01L21/30625 ,  H01L21/743 ,  H01L21/76243 ,  H01L21/76248 ,  H01L21/76283 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a miniaturized semiconductor device having an SOI layer, in which: a silicon layer is formed over a semiconductor substrate via an BOX film; after the silicon layer is patterned by using a nitride film as a mask, an insulating film covering the surface of each of the nitride film, the silicon layer, and the BOX film is formed; subsequently, an opening, which penetrates the insulating film and the BOX film and which exposes the upper surface of the semiconductor substrate, is formed, and an epitaxial layer is formed in the opening; subsequently, the SOI region and a bulk silicon layer are formed over the semiconductor substrate by flattening the upper surface of the epitaxial layer with the use of the nitride film as an etching stopper film.

Abstract translation: 公开了一种具有SOI层的小型半导体器件，其中：通过BOX膜在半导体衬底上形成硅层; 在通过使用氮化物膜作为掩模对硅层进行图案化之后，形成覆盖氮化物膜，硅层和BOX膜中的每一个的表面的绝缘膜; 随后，形成穿透绝缘膜和BOX膜并露出半导体衬底的上表面的开口，并且在开口中形成外延层; 随后，通过使用氮化物膜作为蚀刻停止膜来平坦化外延层的上表面，在半导体衬底上形成SOI区域和体硅层。

公开(公告)号：US20130069723A1

公开(公告)日：2013-03-21

申请号：US13675820

申请日：2012-11-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tsuyoshi KAWAKAMI ,  Akihiko FURUKAWA ,  Satoshi YAMAKAWA ,  Tetsuya IIDA ,  Masao KONDO ,  Yutaka HOSHINO

IPC: H03F3/26

CPC classification number: H03F3/211 ,  H03F1/56 ,  H03F3/26 ,  H03F2200/537 ,  H03F2203/21139

Abstract: In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.

Abstract translation: 为了实现功率放大电路的频率特性的更宽的带宽，通过二次电感器将分别以不同频率匹配的差分推挽放大器的输出组合在一起，并且输出组合信号。

公开(公告)号：US20210356660A1

公开(公告)日：2021-11-18

申请号：US16874176

申请日：2020-05-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA

IPC: G02B6/122 ,  H04B10/67 ,  G02B6/30

Abstract: A semiconductor device includes a first insulating film, a first optical waveguide and a second optical waveguide. The first insulating film has a first surface and a second surface opposite to the first surface. The first optical waveguide is formed on the first surface of the first insulating film. The second optical waveguide is formed on the second surface of the first insulating film. The second optical waveguide, in plan view, overlaps with an end portion of the first optical waveguide without overlapping with another end portion of the first optical waveguide.

公开(公告)号：US20200161278A1

公开(公告)日：2020-05-21

申请号：US16598806

申请日：2019-10-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi KUWABARA ,  Yasutaka NAKASHIBA ,  Tetsuya IIDA

IPC: H01L25/065 ,  H01L25/00 ,  H03K17/687

Abstract: The control system according to embodiments includes a switching element, a control unit controlling the conductive state of the switching element, and a first capacitor storing charge supplied to the control unit. The first capacitor and the control unit are connected with each other via the switching element.

公开(公告)号：US20190072717A1

公开(公告)日：2019-03-07

申请号：US16036455

申请日：2018-07-16

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA

IPC: G02B6/122 ,  G02B6/125

CPC classification number: G02B6/1228 ,  G02B6/125 ,  G02B2006/12061 ,  G02B2006/12119

Abstract: To provide a semiconductor device including a low-loss optical waveguide. The optical waveguide included in the semiconductor device has a core layer covered with first and second clad layers having respectively different refractive indices. A portion of the core layer is covered at a first ratio, that is, a ratio of the first clad layer to the second clad layer and at the same time, a second ratio, that is, a ratio of the second clad layer to the first clad layer. At this time, the first ratio and the second ratio are each a finite value more than 0.

公开(公告)号：US20190004342A1

公开(公告)日：2019-01-03

申请号：US15976912

申请日：2018-05-11

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA ,  Shinichi KUWABARA

IPC: G02F1/01 ,  G02F1/025

Abstract: In an optical waveguide supplied with electricity by using a heater, miniaturization of the device is achieved by enhancing heat dissipation efficiency and heat resistance. In a modulator including an optical waveguide formed on an insulating film, a first interlayer insulating film that covers the optical waveguide, a heater formed on the first interlayer insulating film, and a second interlayer insulating film that covers the heater, a heat conducting portion adjacent to the optical waveguide and the heater and penetrating the first and second interlayer insulating films is formed.

公开(公告)号：US20180366409A1

公开(公告)日：2018-12-20

申请号：US15954213

申请日：2018-04-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi KUWABARA ,  Tetsuya IIDA ,  Yasutaka NAKASHIBA

IPC: H01L23/522 ,  H01L25/065 ,  H01L23/31 ,  H01L23/528 ,  H01L23/64 ,  H01L23/552 ,  H01L21/8238 ,  H01L25/00

CPC classification number: H01L23/5227 ,  H01L21/26513 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/552 ,  H01L23/645 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2225/0651 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06562 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A compact semiconductor device with an isolator. The semiconductor device includes two chips, namely a first semiconductor chip and a second semiconductor chip which are stacked with the main surfaces of the semiconductor chips partially facing each other. A first coil and a second coil which are formed in the first semiconductor chip and the second semiconductor chip respectively are arranged to face each other so as to be magnetically coupled during operation of the semiconductor device. The pair of first and second coils make up an isolator. The first coil is arranged in a manner to overlap part of the circuit region of the first semiconductor chip in plan view and the second coil is arranged in a manner to overlap part of the circuit region of the second semiconductor chip in plan view.

公开(公告)号：US20180012959A1

公开(公告)日：2018-01-11

申请号：US15700669

申请日：2017-09-11

Applicant: Renesas Electronics Corporation

Inventor： Akio ICHIMURA ,  Satoshi EGUCHI ,  Tetsuya IIDA ,  Yuya ABIKO

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7811

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

公开(公告)号：US20160204192A1

公开(公告)日：2016-07-14

申请号：US14965899

申请日：2015-12-11

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO ,  Satoshi EGUCHI ,  Akio ICHIMURA ,  Natsuo YAMAGUCHI ,  Tetsuya IIDA

IPC: H01L29/06 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/417

CPC classification number: H01L29/0696 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/0688 ,  H01L29/06 ,  H01L29/0634 ,  H01L29/0684 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/66727 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7811

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

Abstract translation: 在包括p型列和n型列周期性排列的超结结构的半导体器件中，形成半导体元件的单元区域中的p型列区的深度比深度 在围绕细胞区域的中间区域中的p型列区域。 由此，电池区域的击穿电压变得低于中间区域的击穿电压。 即使在产生雪崩电流的电池区域中，优先发生雪崩击穿现象，电流分散而平稳地流动。 由此，能够避免局部的电流收缩和附带的断线，能够提高雪崩电阻（半导体装置的崩溃电流量的破坏）。