公开(公告)号：US20170018611A1

公开(公告)日：2017-01-19

申请号：US15279565

申请日：2016-09-29

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Abstract translation: 在SOI衬底上的栅电极的侧壁上形成具有通过依次层叠氧化硅膜和氮化物膜而获得的堆叠结构的侧壁。 随后，在栅极旁边形成外延层之后，去除氮化物膜。 然后，使用栅电极和外延层作为掩模，将杂质注入到半导体衬底的上表面中，使得仅在半导体衬底的上表面的正下方形成晕圈区域 栅电极的两端附近。

公开(公告)号：US20130140669A1

公开(公告)日：2013-06-06

申请号：US13691800

申请日：2012-12-02

Applicant: Renesas Electronics Corporation

Inventor： Jiro YUGAMI ,  Toshiaki IWAMATSU ,  Katsuyuki HORITA ,  Hideki MAKIYAMA ,  Yasuo INOUE ,  Yoshiki YAMAMOTO

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649

Abstract: A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film.

Abstract translation: 在SOI衬底上形成作为半导体元件的第一MISFET。 SOI衬底包括作为基底的支撑衬底，BOX层，其是形成在支撑衬底的主表面（表面）上的绝缘层，即掩埋氧化物膜; 以及作为在BOX层上形成的半导体层的SOI层。 作为半导体元件的第一MISFET形成于SOI层。 在隔离区域中，穿过SOI层和BOX层形成隔离槽，使得槽的底面位于支撑基板的厚度的中间。 隔离膜被埋在正在形成的隔离槽中。 然后，在BOX层和隔离膜之间插入抗氧化膜。

公开(公告)号：US20130119470A1

公开(公告)日：2013-05-16

申请号：US13678103

申请日：2012-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsuyuki HORITA ,  Toshiaki IWAMATSU ,  Hideki MAKIYAMA ,  Yoshiki YAMAMOTO

IPC: H01L29/78 ,  H01L21/48

CPC classification number: H01L21/84 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/486 ,  H01L21/743 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/78648 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.

公开(公告)号：US20210257459A1

公开(公告)日：2021-08-19

申请号：US17224743

申请日：2021-04-07

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/265 ,  H01L29/06 ,  H01L21/74 ,  H01L21/8234

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.
A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20200066757A1

公开(公告)日：2020-02-27

申请号：US16670918

申请日：2019-10-31

Applicant: Renesas Electronics Corporation

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20180019260A1

公开(公告)日：2018-01-18

申请号：US15695410

申请日：2017-09-05

Applicant: Renesas Electronics Corporation

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417

CPC classification number: H01L27/1203 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/1207 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20160372486A1

公开(公告)日：2016-12-22

申请号：US15251238

申请日：2016-08-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuta TSUCHIYA ,  Toshiaki IWAMATSU

IPC: H01L27/12 ,  H01L27/11 ,  H01L21/84 ,  H01L29/06

Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

公开(公告)号：US20160156350A1

公开(公告)日：2016-06-02

申请号：US15018533

申请日：2016-02-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuta TSUCHIYA ,  Toshiaki IWAMATSU

IPC: H03K17/687

CPC classification number: H01L27/1203 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H03K17/6872

Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

公开(公告)号：US20160118476A1

公开(公告)日：2016-04-28

申请号：US14990242

申请日：2016-01-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takaaki TSUNOMURA ,  Toshiaki IWAMATSU

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L29/06

CPC classification number: H01L29/66537 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/66492 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/78603 ,  H01L29/78684

Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.

Abstract translation: 具有在包括支撑衬底的SOI衬底上形成的n沟道MISFET的半导体器件，形成在支撑衬底上的绝缘层和形成在绝缘层上的硅层具有以下结构。 在栅电极的支撑基板上设置用于阈值调整的杂质区域，使得硅层含有碳。 可以通过半导体区域以这种方式调整阈值进行阈值调整。 此外，通过设置含有碳的硅层，即使当用于阈值调节的半导体区域的杂质扩散到穿过绝缘层的硅层时，通过注入到硅层中的碳使杂质失活。 结果，可以降低晶体管特性的波动，例如MISFET的阈值电压的波动。

公开(公告)号：US20160043717A1

公开(公告)日：2016-02-11

申请号：US14919644

申请日：2015-10-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki MAKIYAMA ,  Toshiaki IWAMATSU

IPC: H03K17/687 ,  H01L27/12

CPC classification number: H03K17/687 ,  G05F1/625 ,  H01L27/1203 ,  H01L29/78 ,  H03K2217/0018

Abstract: A semiconductor integrated circuit device has, as a current monitor circuit, a circuit in which n-channel type MISFETs are connected in series with each other. Based on a delay time of a speed monitor circuit in a state where a substrate bias is being applied to the p-channel type MISFETs, a first voltage value of a first substrate bias to be applied to the p-channel type MISFETs is determined. Next, based on a current flowing through an n-channel type MISFET in a state where the first substrate bias is being applied to the p-channel type MISFETs of the current monitor circuit and a second substrate bias is being applied to the n-channel type MISFETs of the current monitor circuit, a second voltage value of the second substrate bias to be applied to the n-channel type MISFETs is determined.

Abstract translation: 作为电流监视电路，半导体集成电路器件具有其中n沟道型MISFET彼此串联连接的电路。 基于将衬底偏压施加到p沟道型MISFET的状态下的速度监视器电路的延迟时间，确定要施加到p沟道型MISFET的第一衬底偏置的第一电压值。 接下来，基于在第一衬底偏压被施加到电流监视电路的p沟道型MISFET的状态下流过n沟道型MISFET的电流，并且第二衬底偏置被施加到n沟道 确定要施加到n沟道型MISFET的第二衬底偏置的第二电压值。