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    SEMICONDUCTOR DEVICE
    21.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190326432A1

    公开(公告)日：2019-10-24

    申请号：US16371989

    申请日：2019-04-01

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yoshito NAKAZAWA

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/40

    Abstract: A semiconductor device includes: a cell region provided in a main surface of a semiconductor substrate composed of a crystal plane (100); a field insulating film embedded in the semiconductor substrate; and an annular p-type well region surrounding the cell region. The p-type well region includes a first region extending in a direction, a second region extending in a direction, and a third region connecting the first region and the second region and having an arc shape in plan view. The field insulating film has an opening provided in the p-type well region and extending along the p-type well region in plan view. The opening includes a first opening extending in the direction in the first region and a second opening extending in the direction in the second region, and the first opening and the second opening are divided from each other in the third region.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
    22.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20170040445A1

    公开(公告)日：2017-02-09

    申请号：US15333430

    申请日：2016-10-25

    Applicant: Renesas Electronics Corporation

    Inventor： Yoshito NAKAZAWA ,  Yuji YATSUDA

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

    CPC classification number: H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

    Abstract: A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode.

    Abstract translation: 一种具有场效应晶体管的半导体器件，包括半导体衬底中的沟槽，沟槽中的第一绝缘膜，第一绝缘膜上的本征多晶硅膜，以及本征多晶硅膜中的第一导电型杂质，以形成 第一导电膜。 蚀刻第一导电膜以在沟槽中形成第一栅电极。 在第二绝缘膜上形成有在第一绝缘膜和第一栅电极上方的沟槽中的第二绝缘膜，并且在第二绝缘膜上形成杂质浓度高于第一栅电极的第一导电型掺杂多晶硅膜。 掺杂多晶硅膜设置在沟槽的上部，以形成第二栅电极。

    POWER SEMICONDUCTOR DEVICE
    23.
    发明申请
    POWER SEMICONDUCTOR DEVICE 审中-公开
    功率半导体器件

    公开(公告)号：US20150097237A1

    公开(公告)日：2015-04-09

    申请号：US14569730

    申请日：2014-12-14

    Applicant: Renesas Electronics Corporation

    Inventor： Tomohiro TAMAKI ,  Yoshito NAKAZAWA

    IPC: H01L29/78 ,  H01L29/06

    CPC classification number: H01L29/0634 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66681 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7825

    Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.

    Abstract translation: 解决了与各种工艺参数相对较轻的波动引起的n沟道功率MOSFET等相关的问题：源极 - 漏极击穿电压通过靠近p型体区域的端部的击穿而减小 到由该区域的电场浓度引起的活性单元区域与芯片周边部分之间的环状中间区域附近的部分。 为了解决这个问题，在第一导电类型的有源电池区域，芯片外围区域和位于它们之间的中间区域的各个漂移区域中，具有超结构结构的功率半导体器件采取以下措施： 使包括中间区域中的超结构结构的第二导电类型的列区域中的至少一个比其它区域的宽度大。

    SEMICONDUCTOR DEVICE INCLUDING A MOSFET AND SCHOTTKY JUNCTION
    27.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING A MOSFET AND SCHOTTKY JUNCTION 有权
    包括MOSFET和肖特基结的半导体器件

    公开(公告)号：US20130214378A1

    公开(公告)日：2013-08-22

    申请号：US13844950

    申请日：2013-03-16

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Nobuyuki SHIRAI ,  Nobuyoshi MATSUURA ,  Yoshito NAKAZAWA

    IPC: H01L29/872

    CPC classification number: H01L29/7806 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/20 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/475 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/7823 ,  H01L29/872 ,  H01L29/8725

    Abstract: A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes.

    Abstract translation: 用于电源电路的半导体器件具有第一和第二MOSFET。 MOSFET之一的源极 - 漏极路径耦合到另一个MOSFET的源极 - 漏极路径，并且负载元件耦合到源极 - 漏极路径的连接节点。 第二MOSFET形成在具有肖特基势垒二极管的半导体衬底上。 第二MOSFET的第一栅电极形成在半导体衬底的第一区域中的沟槽中，而第二MOSFET的第二栅电极形成在半导体衬底的第二区域中的沟槽中。 第一和第二栅极电连接在一起。 在相邻的第二栅电极之间形成肖特基势垒二极管的部分。 相邻的第一栅电极之间的中心到中心的间隔小于相邻的第二栅电极之间的中心间距。

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