Patent search ap:("RENESAS ELECTRONICS CORPORATION") AND inv:"Nobuyoshi MATSUURA" Page 1

1.

发明申请
SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME 有权
Title translation: 半导体器件及其制造方法

公开(公告)号：US20170005089A1

公开(公告)日：2017-01-05

申请号：US15265940

申请日：2016-09-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masaki SHIRAISHI , Tomoaki UNO , Nobuyoshi MATSUURA

IPC: H01L27/06 , H01L21/8234 , H01L21/28 , H02M3/155 , H01L29/49 , H01L29/423 , H02M7/00 , H01L29/66 , H01L29/45

CPC classification number: H01L27/0629 , H01L21/28035 , H01L21/823475 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L29/1095 , H01L29/41741 , H01L29/4232 , H01L29/4236 , H01L29/4238 , H01L29/45 , H01L29/456 , H01L29/4916 , H01L29/66143 , H01L29/66734 , H01L29/7806 , H01L29/7813 , H01L29/872 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/45015 , H01L2224/45144 , H01L2224/48011 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/48253 , H01L2224/48624 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2224/73221 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/20753 , H01L2924/20755 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H02M3/155 , H02M7/003

Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Abstract translation: 在具有功率MOS·FET高侧开关和功率MOS·FET低侧开关串联的电路的非绝缘DC-DC转换器中，功率MOS·FET低侧开关和肖特基与功率MOS·FET低侧开关并联连接的二极管形成在一个半导体芯片内。肖特基势垒二极管的形成区域SDR设置在半导体芯片的较短方向的中央，并且在其两侧设置功率MOS·FET低侧开关的形成区域。从半导体芯片的主表面的两长边附近的栅极指向肖特基势垒二极管的形成区域SDR，设置多个栅极指，以便在它们之间插入形成区域SDR。

2.

发明申请
SEMICONDUCTOR DEVICE 审中-公开

公开(公告)号：US20160109896A9

公开(公告)日：2016-04-21

申请号：US13727680

申请日：2012-12-27

Applicant: Renesas Electronics Corporation

Inventor： Masaki SHIRAISHI , Noboru AKIYAMA , Tomoaki UNO , Nobuyoshi MATSUURA

IPC: G05F3/08

CPC classification number: G05F3/08 , H01L23/3107 , H01L23/4824 , H01L23/49551 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/072 , H01L25/16 , H01L29/1095 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4238 , H01L29/7811 , H01L29/7813 , H01L29/7835 , H01L2224/05554 , H01L2224/05644 , H01L2224/05647 , H01L2224/0603 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/48644 , H01L2224/48647 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2224/49431 , H01L2224/73221 , H01L2224/84801 , H01L2224/8485 , H01L2224/85375 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01056 , H01L2924/01059 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/07802 , H01L2924/12032 , H01L2924/12036 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H02M7/003 , H01L2924/00014 , H01L2924/00 , H01L2924/00012

Abstract: In order to reduce parasitic inductance of a main circuit in a power supply circuit, a non-insulated DC-DC converter is provided having a circuit in which a power MOS·FET for a high-side switch and a power MOS·FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS·FET for the high-side switch is formed by a p channel vertical MOS·FET, and the power MOS·FET for the low-side switch is formed by an n channel vertical MOS·FET. Thus, a semiconductor chip formed with the power MOS·FET for the high-side switch and a semiconductor chip formed with the power MOS·FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.

3.

发明申请
SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME 有权
Title translation: 半导体器件及其制造方法

公开(公告)号：US20140054692A1

公开(公告)日：2014-02-27

申请号：US14072047

申请日：2013-11-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masaki SHIRAISHI , Tomoaki UNO , Nobuyoshi MATSUURA

IPC: H01L29/78

CPC classification number: H01L27/0629 , H01L21/28035 , H01L21/823475 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L29/1095 , H01L29/41741 , H01L29/4232 , H01L29/4236 , H01L29/4238 , H01L29/45 , H01L29/456 , H01L29/4916 , H01L29/66143 , H01L29/66734 , H01L29/7806 , H01L29/7813 , H01L29/872 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/45015 , H01L2224/45144 , H01L2224/48011 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/48253 , H01L2224/48624 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2224/73221 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/20753 , H01L2924/20755 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H02M3/155 , H02M7/003

Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Abstract translation: 在具有电源MOS.FET高侧开关和功率MOS.FET低侧开关串联连接的电路的非绝缘DC-DC转换器中，功率MOS.FET低侧开关和肖特基与功率MOS.FET低侧开关并联连接的阻挡二极管形成在一个半导体芯片内。肖特基势垒二极管的形成区域SDR设置在半导体芯片的较短方向的中心，并且在其两侧设置功率MOS.FET低侧开关的形成区域。从半导体芯片的主表面的两长边附近的栅极指向肖特基势垒二极管的形成区域SDR，设置多个栅极指，以便在它们之间插入形成区域SDR。

4.

发明申请
SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME 有权
Title translation: 半导体器件及其制造方法

公开(公告)号：US20160005854A1

公开(公告)日：2016-01-07

申请号：US14857596

申请日：2015-09-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masaki SHIRAISHI , Tomoaki UNO , Nobuyoshi MATSUURA

IPC: H01L29/78 , H02M7/00

CPC classification number: H01L27/0629 , H01L21/28035 , H01L21/823475 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L29/1095 , H01L29/41741 , H01L29/4232 , H01L29/4236 , H01L29/4238 , H01L29/45 , H01L29/456 , H01L29/4916 , H01L29/66143 , H01L29/66734 , H01L29/7806 , H01L29/7813 , H01L29/872 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/45015 , H01L2224/45144 , H01L2224/48011 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/48253 , H01L2224/48624 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2224/73221 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/20753 , H01L2924/20755 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H02M3/155 , H02M7/003

Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Abstract translation: 在具有功率MOS·FET高侧开关和功率MOS·FET低侧开关串联的电路的非绝缘DC-DC转换器中，功率MOS·FET低侧开关和肖特基与功率MOS·FET低侧开关并联连接的二极管形成在一个半导体芯片内。肖特基势垒二极管的形成区域SDR设置在半导体芯片的较短方向的中央，并且在其两侧设置功率MOS·FET低侧开关的形成区域。从半导体芯片的主表面的两长边附近的栅极指向肖特基势垒二极管的形成区域SDR，设置多个栅极指，以便在它们之间插入形成区域SDR。

5.

发明申请
Semiconductor Device 有权
Title translation: 半导体器件

公开(公告)号：US20140312510A1

公开(公告)日：2014-10-23

申请号：US14322320

申请日：2014-07-02

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro SATOU , Tomoaki UNO , Nobuyoshi MATSUURA , Masaki SHIRAISHI

IPC: H01L23/538

CPC classification number: H01L23/5386 , H01L23/49575 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L25/165 , H01L29/4175 , H01L2224/05554 , H01L2224/0603 , H01L2224/29339 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2224/4943 , H01L2224/83855 , H01L2224/85 , H01L2224/85203 , H01L2224/85205 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/0102 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/20753 , H01L2924/20755 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H02M3/1588 , H05K7/02 , Y02B70/1466 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/2075 , H01L2924/20754

Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Abstract translation: 本发明提供一种具有电路的非绝缘型DC-DC转换器，其中用于高侧开关的功率MOS•FET和低边开关的功率MOS•FET串联连接。在非绝缘型DC-DC转换器中，用于高侧开关的功率晶体管，低边开关的功率晶体管和驱动它们的驱动电路分别由不同的半导体芯片构成。三个半导体芯片被容纳在一个封装中，并且包括用于高侧开关的功率晶体管的半导体芯片和包括驱动电路的半导体芯片被布置成彼此接近。

6.

发明申请
SEMICONDUCTOR DEVICE 有权
Title translation: 半导体器件

公开(公告)号：US20130203217A1

公开(公告)日：2013-08-08

申请号：US13717464

申请日：2012-12-17

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro SATOU , Tomoaki UNO , Nobuyoshi MATSUURA , Masaki SHIRAISHI

IPC: H01L23/00

CPC classification number: H01L23/5386 , H01L23/49575 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L25/165 , H01L29/4175 , H01L2224/05554 , H01L2224/0603 , H01L2224/29339 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2224/4943 , H01L2224/83855 , H01L2224/85 , H01L2224/85203 , H01L2224/85205 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/0102 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/20753 , H01L2924/20755 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H02M3/1588 , H05K7/02 , Y02B70/1466 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/2075 , H01L2924/20754

Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Abstract translation: 本发明提供一种具有电路的非绝缘型DC-DC转换器，其中用于高侧开关的功率MOS.FET和用于低侧开关的功率MOS.FET串联连接。在非绝缘型DC-DC转换器中，用于高侧开关的功率晶体管，低边开关的功率晶体管和驱动它们的驱动电路分别由不同的半导体芯片构成。三个半导体芯片被容纳在一个封装中，并且包括用于高侧开关的功率晶体管的半导体芯片和包括驱动电路的半导体芯片被布置成彼此接近。

7.

发明申请
SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME 有权
Title translation: 半导体器件及其制造方法

公开(公告)号：US20140332878A1

公开(公告)日：2014-11-13

申请号：US14340198

申请日：2014-07-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masaki SHIRAISHI , Tomoaki UNO , Nobuyoshi MATSUURA

IPC: H01L29/78 , H02M7/00 , H01L23/495

CPC classification number: H01L27/0629 , H01L21/28035 , H01L21/823475 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L29/1095 , H01L29/41741 , H01L29/4232 , H01L29/4236 , H01L29/4238 , H01L29/45 , H01L29/456 , H01L29/4916 , H01L29/66143 , H01L29/66734 , H01L29/7806 , H01L29/7813 , H01L29/872 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/45015 , H01L2224/45144 , H01L2224/48011 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/48253 , H01L2224/48624 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2224/73221 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/20753 , H01L2924/20755 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H02M3/155 , H02M7/003

Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Abstract translation: 在具有功率MOS·FET高侧开关和功率MOS·FET低侧开关串联的电路的非绝缘DC-DC转换器中，功率MOS·FET低侧开关和肖特基与功率MOS·FET低侧开关并联连接的二极管形成在一个半导体芯片内。肖特基势垒二极管的形成区域SDR设置在半导体芯片的较短方向的中央，并且在其两侧设置功率MOS·FET低侧开关的形成区域。从半导体芯片的主表面的两长边附近的栅极指向肖特基势垒二极管的形成区域SDR，设置多个栅极指，以便在它们之间插入形成区域SDR。

8.

发明申请
Semiconductor Device 有权
Title translation: 半导体器件

公开(公告)号：US20140003002A1

公开(公告)日：2014-01-02

申请号：US14014286

申请日：2013-08-29

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro SATOU , Tomoaki UNO , Nobuyoshi MATSUURA , Masaki SHIRAISHI

IPC: H05K7/02

CPC classification number: H01L23/5386 , H01L23/49575 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L25/165 , H01L29/4175 , H01L2224/05554 , H01L2224/0603 , H01L2224/29339 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2224/4943 , H01L2224/83855 , H01L2224/85 , H01L2224/85203 , H01L2224/85205 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/0102 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/20753 , H01L2924/20755 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H02M3/1588 , H05K7/02 , Y02B70/1466 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/2075 , H01L2924/20754

Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Abstract translation: 本发明提供一种具有电路的非绝缘型DC-DC转换器，其中用于高侧开关的功率MOS.FET和用于低侧开关的功率MOS.FET串联连接。在非绝缘型DC-DC转换器中，用于高侧开关的功率晶体管，低边开关的功率晶体管和驱动它们的驱动电路分别由不同的半导体芯片构成。三个半导体芯片被容纳在一个封装中，并且包括用于高侧开关的功率晶体管的半导体芯片和包括驱动电路的半导体芯片被布置成彼此接近。

9.

发明申请
SEMICONDUCTOR DEVICE INCLUDING A MOSFET AND SCHOTTKY JUNCTION 有权
Title translation: 包括MOSFET和肖特基结的半导体器件

公开(公告)号：US20130214378A1

公开(公告)日：2013-08-22

申请号：US13844950

申请日：2013-03-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nobuyuki SHIRAI , Nobuyoshi MATSUURA , Yoshito NAKAZAWA

IPC: H01L29/872

CPC classification number: H01L29/7806 , H01L27/0629 , H01L29/0615 , H01L29/0619 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/20 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/475 , H01L29/7802 , H01L29/7811 , H01L29/7813 , H01L29/782 , H01L29/7823 , H01L29/872 , H01L29/8725

Abstract: A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes.

Abstract translation: 用于电源电路的半导体器件具有第一和第二MOSFET。 MOSFET之一的源极 - 漏极路径耦合到另一个MOSFET的源极 - 漏极路径，并且负载元件耦合到源极 - 漏极路径的连接节点。第二MOSFET形成在具有肖特基势垒二极管的半导体衬底上。第二MOSFET的第一栅电极形成在半导体衬底的第一区域中的沟槽中，而第二MOSFET的第二栅电极形成在半导体衬底的第二区域中的沟槽中。第一和第二栅极电连接在一起。在相邻的第二栅电极之间形成肖特基势垒二极管的部分。相邻的第一栅电极之间的中心到中心的间隔小于相邻的第二栅电极之间的中心间距。