公开(公告)号：US09263291B2

公开(公告)日：2016-02-16

申请号：US14079120

申请日：2013-11-13

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Hiraku Chakihara ,  Yoshiyuki Kawashima ,  Kentaro Saito ,  Takashi Hashimoto

IPC: H01L21/44 ,  H01L21/3105 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115 ,  H01L21/8234

CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。

公开(公告)号：US20160027651A1

公开(公告)日：2016-01-28

申请号：US14801798

申请日：2015-07-16

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Kentaro Saito ,  Hiraku Chakihara

IPC: H01L21/28 ,  H01L29/40 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L21/02164 ,  H01L21/0217 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/401 ,  H01L29/42344 ,  H01L29/66833

Abstract: The present invention improves the performance of a semiconductor device. In a manufacturing method of a semiconductor device, sacrificial oxide films are formed over the side surface of a control gate electrode formed in a memory cell region, the surface of a cap insulating film formed in the memory cell region, and the surface of the part, which remains in a peripheral circuit region, of an insulating film. The step of forming the sacrificial oxide films includes the steps of: oxidizing the side surface of the control gate electrode by a thermal oxidation method; and oxidizing the surface of the cap insulating film and the surface of the part, which remains in the peripheral circuit region, of the insulating film by an ISSG oxidation method.

Abstract translation: 本发明改进了半导体器件的性能。 在半导体器件的制造方法中，在形成在存储单元区域中的控制栅电极的侧表面上形成牺牲氧化物膜，形成在存储单元区域中的帽绝缘膜的表面和部件的表面 ，其保留在绝缘膜的外围电路区域中。 形成牺牲氧化膜的步骤包括以下步骤：通过热氧化法氧化控制栅电极的侧表面; 并通过ISSG氧化法氧化绝缘膜上的帽绝缘膜的表面和保留在外围电路区域中的部分的表面。

公开(公告)号：US08975678B2

公开(公告)日：2015-03-10

申请号：US13867213

申请日：2013-04-22

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Koichi Toba ,  Yasushi Ishii ,  Toshikazu Matsui ,  Takashi Hashimoto

IPC: H01L49/02 ,  H01L27/06 ,  H01L27/08 ,  H01L27/105 ,  H01L27/115

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  H01L28/40

Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

Abstract translation: 关于包括电容器元件的半导体器件，提供了一种能够提高电容器元件的可靠性的技术。 电容器元件形成在半导体衬底上形成的元件隔离区域中。 电容器元件包括通过电容器绝缘膜形成在下电极上的下电极和上电极。 基本上，下电极和上电极由形成在多晶硅膜的表面上的多晶硅膜和硅化钴膜形成。 形成在上电极上的钴硅化物膜的端部与上电极的端部间隔开一定距离。 此外，形成在下电极上的钴硅化物膜的端部与上电极和下电极之间的边界间隔一定距离。

公开(公告)号：US12302610B2

公开(公告)日：2025-05-13

申请号：US17969904

申请日：2022-10-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi Maeda ,  Yoshiyuki Kawashima

IPC: H10D30/69 ,  H10D30/68

Abstract: A height of an upper surface of a control gate electrode is lower than a highest position of a lower surface of a silicide layer on a memory gate electrode adjacent to the control gate electrode via an ONO film. As a result, a structure in contact with the ONO film between the control gate electrode and the memory gate electrode is only the control gate electrode and the memory gate electrode made of polysilicon.

公开(公告)号：US11942163B2

公开(公告)日：2024-03-26

申请号：US17502832

申请日：2021-10-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki Kawashima

IPC: G11C16/28 ,  G06N3/063 ,  G11C11/54 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  H01L29/423 ,  H01L29/792

CPC classification number: G11C16/28 ,  G06N3/063 ,  G11C11/54 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/16 ,  H01L29/4234 ,  H01L29/792

Abstract: In a case of achievement of a neural network circuit using a plurality of nonvolatile memory cells, a technique capable of accurately reading information recorded in the plurality of nonvolatile memory cells is provided. A semiconductor device includes: a plurality of nonvolatile memory cells; a plurality of reference-current cells; and a sense amplifier comparing an electric current flowing in each of the plurality of nonvolatile memory cells and an electric current flowing in each of the plurality of reference-current cells. In this case, each cross-sectional structure of the plurality of reference-current cells is the same as each cross-sectional structure of the plurality of nonvolatile memory cells. The writing operation or the erasing operation is also performed to each of the plurality of reference-current memory cells when the writing operation or the erasing operation is performed to each of the plurality of nonvolatile memory cells.

公开(公告)号：US10818679B2

公开(公告)日：2020-10-27

申请号：US16460476

申请日：2019-07-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Digh Hisamoto ,  Yoshiyuki Kawashima

IPC: H01L27/11521 ,  H01L21/8234 ,  H01L27/1158 ,  H01L27/11565 ,  H01L27/11568

Abstract: In a MONOS memory of the split-gate type formed by a field effect transistor formed on a fin, it is prevented that the rewrite lifetime of the MONOS memory is reduced due to charges being locally transferred into and out of an ONO film in the vicinity of the top of the fin by repeating the write operation and the erase operation. By forming a source region at a position spaced downward from a first upper surface of the fin in a region directly below a memory gate electrode, the current is prevented from flowing concentratedly at the upper end of the fin.

公开(公告)号：US10312252B2

公开(公告)日：2019-06-04

申请号：US15486741

申请日：2017-04-13

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima

IPC: H01L29/08 ,  H01L21/28 ,  H01L27/11568 ,  H01L21/265 ,  H01L21/324 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: A method of manufacturing a semiconductor device having a memory cell for a split-gate MONOS memory with a halo region, which prevents miswriting in the memory cell and worsening of short channel characteristics. In the method, a first diffusion layer of a drain region and a second diffusion layer of a source region in the memory cell for the MONOS memory are formed in different ion implantation steps. The steps are carried out so that the first diffusion layer has a smaller formation depth than the second diffusion layer. After the formation of the layers, the impurities inside the first and second diffusion layers are diffused by heat treatment to form a first diffusion region and a second diffusion region.

公开(公告)号：US10002768B2

公开(公告)日：2018-06-19

申请号：US15796621

申请日：2017-10-27

Applicant: Renesas Electronics Corporation

Inventor： Kentaro Saito ,  Hideki Sugiyama ,  Hiraku Chakihara ,  Yoshiyuki Kawashima

IPC: H01L21/28 ,  H01L49/02 ,  H01L27/11573 ,  H01L27/06 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L29/40117 ,  H01L27/0629 ,  H01L27/11573 ,  H01L28/60 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device, a memory cell is formed of a control gate electrode and a memory gate electrode adjacent to each other, a gate insulating film formed below the control gate electrode and an insulating film formed below the memory gate electrode and having a charge accumulating part therein. Also, in this semiconductor device, a capacitive element is formed of a lower electrode, an upper electrode and a capacitive insulating film formed between the upper electrode and the lower electrode. A thickness of the lower electrode is smaller than a thickness of the control gate electrode.

公开(公告)号：US09722096B2

公开(公告)日：2017-08-01

申请号：US14872089

申请日：2015-09-30

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Shoji Yoshida

IPC: H01L21/336 ,  H01L29/792 ,  H01L21/28 ,  H01L21/30 ,  H01L21/324 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/7923 ,  H01L21/28176 ,  H01L21/28282 ,  H01L21/3003 ,  H01L21/324 ,  H01L27/11573 ,  H01L29/513 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device including a nonvolatile memory cell and a field effect transistor together is improved in performance. In a method of manufacturing a semiconductor device, a hydrogen-containing insulating film is formed before heat treatment of a semiconductor wafer, the hydrogen-containing insulating film covering a gate electrode and agate insulating film in a region that will have a memory cell therein, and exposing a region that will have therein a MISFET configuring a peripheral circuit. Consequently, hydrogen in the hydrogen-containing insulating film is diffused into an interface between the gate insulating film and the semiconductor substrate, and thereby a defect at the interface is selectively repaired.

公开(公告)号：US09373630B2

公开(公告)日：2016-06-21

申请号：US14989999

申请日：2016-01-07

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Hiraku Chakihara ,  Yoshiyuki Kawashima ,  Kentaro Saito ,  Takashi Hashimoto

IPC: H01L21/8234 ,  H01L27/115 ,  H01L27/092

CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract translation: 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。