公开(公告)号：US20240361799A1

公开(公告)日：2024-10-31

申请号：US18635817

申请日：2024-04-15

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC: G06F1/08 ,  G06F1/10 ,  G06F13/16 ,  H03L7/07 ,  H03L7/081 ,  H03L7/099 ,  H04L7/00 ,  H04L7/10

CPC classification number: G06F1/08 ,  G06F1/10 ,  G06F13/1673 ,  G06F13/1689 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0995 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/10 ,  Y02D10/00

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

公开(公告)号：US11973153B2

公开(公告)日：2024-04-30

申请号：US17445371

申请日：2021-08-18

Applicant: Rambus Inc.

Inventor： Yohan Frans ,  Simon Li ,  John Eric Linstadt ,  Jun Kim

IPC: H01L31/0236 ,  G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F13/16 ,  G06F13/372

CPC classification number: H01L31/02366 ,  G06F3/0613 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1684 ,  G06F13/372 ,  G06F12/00 ,  G06F13/16 ,  Y02D10/00

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

公开(公告)号：US11378998B2

公开(公告)日：2022-07-05

申请号：US17102119

申请日：2020-11-23

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC: G06F1/00 ,  G06F1/08 ,  H03L7/099 ,  H04L7/00 ,  H03L7/081 ,  H03L7/07 ,  H04L7/10 ,  G06F13/16 ,  G06F1/10

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

公开(公告)号：US20180095916A1

公开(公告)日：2018-04-05

申请号：US15702987

申请日：2017-09-13

Applicant: Rambus Inc.

Inventor： Jared LeVan Zerbe ,  Kevin S. Donnelly ,  Stefanos Sidiropoulos ,  Donald C. Stark ,  Mark A. Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno W. Garlepp ,  Tsyr-Chyang Ho ,  Benedict Chung-Kwong Lau

IPC: G06F13/364 ,  G06F13/42 ,  G06F1/10 ,  G06F3/06 ,  G06F12/02 ,  G11C7/10

CPC classification number: G06F13/364 ,  G06F1/10 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/404 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C7/1045 ,  H04L7/0008 ,  H04L7/033

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

公开(公告)号：US09785589B2

公开(公告)日：2017-10-10

申请号：US15222987

申请日：2016-07-29

Applicant: Rambus Inc.

Inventor： Jared LeVan Zerbe ,  Kevin S. Donnelly ,  Stefanos Sidiropoulos ,  Donald C. Stark ,  Mark A. Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno W. Garlepp ,  Tsyr-Chyang Ho ,  Benedict Chung-Kwong Lau

IPC: G06F13/364 ,  G06F13/42 ,  G06F13/40 ,  G06F3/06 ,  G06F1/10 ,  G06F13/16 ,  H04L7/00 ,  G11C7/10 ,  G06F12/02 ,  H04L7/033

CPC classification number: G06F13/364 ,  G06F1/10 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/404 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/7201 ,  G06F2212/7207 ,  G11C7/1045 ,  H04L7/0008 ,  H04L7/033

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

公开(公告)号：US20170177021A1

公开(公告)日：2017-06-22

申请号：US15391299

申请日：2016-12-27

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC: G06F1/08 ,  G06F13/16

CPC classification number: G06F1/08 ,  G06F1/10 ,  G06F13/1673 ,  G06F13/1689 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0995 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/10 ,  Y02D10/14

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

公开(公告)号：US20170147234A1

公开(公告)日：2017-05-25

申请号：US15369244

申请日：2016-12-05

Applicant: Rambus Inc.

Inventor： Yohan Frans ,  Simon Li ,  Eric Linstadt ,  Jun Kim

IPC: G06F3/06 ,  G06F13/372

CPC classification number: H01L31/02366 ,  G06F3/0613 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/0246 ,  G06F13/16 ,  G06F13/1684 ,  G06F13/372 ,  Y02D10/14

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

公开(公告)号：US09564885B2

公开(公告)日：2017-02-07

申请号：US14361575

申请日：2012-11-16

Applicant: Rambus Inc.

Inventor： Pak Shing Chau ,  Wayne S. Richardson ,  Jun Kim

IPC: H03K3/017 ,  H03K5/156 ,  H03K3/012

CPC classification number: H03K5/1565 ,  H03K3/012 ,  H03K3/017

Abstract: Duty cycle error vectors that indicate both the magnitude and direction of the duty cycle error relative to a desired duty cycle are generated within a duty cycle measurement circuit, enabling threshold-based determination of whether duty cycle adjustment is necessary, refraining from power-consuming adjustment and follow-up measurement in those cases where the duty cycle is within a target range. When duty cycle adjustment is deemed necessary, the magnitude of the duty cycle error indicated by the duty cycle error vector may be applied to effect proportional rather than incremental duty cycle adjustment, quickly returning the clock duty cycle to a target range.

Abstract translation: 在占空比测量电路内产生指示相对于期望占空比的占空比误差的大小和方向的占空比误差矢量，使得能够基于阈值确定是否需要占空比调整，避免功耗调节 在占空比在目标范围内的情况下进行跟踪测量。 当认为有必要进行占空比调整时，由占空比误差矢量表示的占空比误差的大小可以用于实现比例而不是增量占空比调整，从而快速地将时钟占空比返回到目标范围。

公开(公告)号：US09515204B2

公开(公告)日：2016-12-06

申请号：US13804334

申请日：2013-03-14

Applicant: Rambus Inc.

Inventor： Yohan Frans ,  Simon Li ,  Eric Lindstadt ,  Jun Kim

IPC: G06F12/02 ,  H01L31/0236 ,  G06F12/00 ,  G06F13/16

CPC classification number: H01L31/02366 ,  G06F3/0613 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/0246 ,  G06F13/16 ,  G06F13/1684 ,  G06F13/372 ,  Y02D10/14

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

Abstract translation: 存储器控制器包括用于将存储器命令发送到与存储器控制器相关联的多个存储器件的命令接口。 存储器控制器还包括确认界面，用于通过耦合在存储器控制器和多个存储器件之间的共享确认链路从多个存储器设备接收确认状态分组，该确认状态分组指示该命令是否被多个 的存储器件。 此外，存储器控制器包括存储器控制器核心，用于对确认状态分组进行解码，以识别对应于多个存储器设备中的每一个的确认状态分组的一部分。

公开(公告)号：US09235537B2

公开(公告)日：2016-01-12

申请号：US13656498

申请日：2012-10-19

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC: G06F1/00 ,  G06F13/16 ,  H03L7/099 ,  H04L7/00 ,  H03L7/081 ,  H03L7/07 ,  H04L7/10

CPC classification number: G06F1/08 ,  G06F1/10 ,  G06F13/1673 ,  G06F13/1689 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0995 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/10 ,  Y02D10/14

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

Abstract translation: 一种存储器系统，其中通过测量在具有低于第一定时的频率的第二定时信号中出现的实际相位延迟来确定在存储器件中用于数据传输的第一定时信号的分配中将发生的定时漂移 并且分布在模拟第一定时信号的分布的至少一部分的漂移特性的一个或多个电路中。 实际的相位延迟在存储器件中确定并提供给存储器控制器，使得用于数据传输的定时信号的相位可以基于所确定的定时漂移来调整。