公开(公告)号：US20110127493A1

公开(公告)日：2011-06-02

申请号：US12627120

申请日：2009-11-30

申请人： Cyril Cabral, JR. ,  Josephine B. Chang ,  Alfred Grill ,  Michael A. Guillorn ,  Christian Lavoie ,  Eugene J. O'Sullivan

发明人： Cyril Cabral, JR. ,  Josephine B. Chang ,  Alfred Grill ,  Michael A. Guillorn ,  Christian Lavoie ,  Eugene J. O'Sullivan

IPC分类号： H01L29/66 ,  H01L21/336

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L29/16 ,  H01L29/1602 ,  H01L51/0048 ,  H01L51/0541 ,  H01L51/105

摘要： A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.

摘要翻译： 场效应晶体管包括金属碳化物源部分，金属碳化物漏极部分，将金属碳化物源部分与金属碳化物部分分离的绝缘碳部分，形成在绝缘和碳部分上的纳米结构，并将金属碳化物源部分连接到 金属碳化物排出部分和形成在绝缘碳部分的至少一部分和至少一部分纳米结构上的栅堆叠。

公开(公告)号：US20110084393A1

公开(公告)日：2011-04-14

申请号：US12967633

申请日：2010-12-14

申请人： Cyril Cabral, JR. ,  Hariklia Deligianni ,  Randolph F. Knarr ,  Sandra G. Malhotra ,  Stephen Rossnagel ,  Xiaoyan Shao ,  Anna Topol ,  Philippe M. Vereecken

发明人： Cyril Cabral, JR. ,  Hariklia Deligianni ,  Randolph F. Knarr ,  Sandra G. Malhotra ,  Stephen Rossnagel ,  Xiaoyan Shao ,  Anna Topol ,  Philippe M. Vereecken

IPC分类号： H01L23/48

CPC分类号： H01L23/485 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact metallurgy structure comprising a patterned dielectric layer having vias on a substrate; a silicide layer of cobalt and/or nickel located at the bottom of vias; a contact layer comprising Ti located in vias on top of the silicide layer; a diffusion layer located in vias and on top of the contact layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer comprises at least one member selected from the group consisting of copper, ruthenium, rhodium platinum, palladium, iridium, rhenium, tungsten, gold, silver and osmium and alloys thereof. When the metal fill layer comprises rhodium, the diffusion layer is not required. Optionally a seed layer for the metal fill layer can be employed.

摘要翻译： 一种接触式冶金结构，包括在衬底上具有通孔的图案化介电层; 位于通孔底部的钴和/或镍的硅化物层; 包含位于硅化物层顶部的通孔中的Ti的接触层; 位于所述接触层的通孔和顶部的扩散层; 提供通孔中的金属填充层以及制造方法。 金属填充层包括选自铜，钌，铑铂，钯，铱，铼，钨，金，银和锇中的至少一种以及它们的合金。 当金属填充层包含铑时，不需要扩散层。 任选地，可以使用用于金属填充层的种子层。

公开(公告)号：US20120261788A1

公开(公告)日：2012-10-18

申请号：US13088083

申请日：2011-04-15

申请人： Qinghuang Lin ,  Benjamin L. Fletcher ,  Cyril Cabral, JR.

发明人： Qinghuang Lin ,  Benjamin L. Fletcher ,  Cyril Cabral, JR.

IPC分类号： H01L29/06 ,  H01L21/28 ,  H01L21/31

CPC分类号： H01L23/5222 ,  H01L21/31127 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/4821 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： Devices and methods for forming a self-aligned airgap interconnect structure includes etching a conductive layer to a substrate to form conductive structures with patterned gaps and filling the gaps with a sacrificial material. The sacrificial material is planarized to expose a top surface of the conductive layer. A permeable cap layer is deposited over the conductive structure and the sacrificial material. Self-aligned airgaps are formed by removing the sacrificial material through the permeable layer.

摘要翻译： 用于形成自对准气隙互连结构的装置和方法包括将导电层蚀刻到衬底以形成具有图案化间隙的导电结构并用牺牲材料填充间隙。 将牺牲材料平坦化以暴露导电层的顶表面。 在导电结构和牺牲材料上沉积可渗透盖层。 通过可渗透层去除牺牲材料形成自对准的气隙。

公开(公告)号：US20110272009A1

公开(公告)日：2011-11-10

申请号：US12775939

申请日：2010-05-07

申请人： Cyril Cabral, JR. ,  Harold J. Hovel ,  Xiaoyan Shao

发明人： Cyril Cabral, JR. ,  Harold J. Hovel ,  Xiaoyan Shao

IPC分类号： H01L31/0288 ,  H01L31/0236 ,  H01L31/18

CPC分类号： H01L31/18 ,  H01L31/022425 ,  Y02E10/50

摘要： A grid stack structure of a solar cell, which includes a silicon substrate, wherein a front side of the silicon is doped with phosphorus to form a n-emitter and a back side of the silicon is screen printed with aluminum (Al) metallization; a dielectric layer, which acts as an antireflection coating (ARC), applied on the silicon; a mask layer applied on the front side to define a grid opening of the dielectric layer, wherein an etching method is applied to open an unmasked grid area; a light-induced plated nickel or cobalt layer applied to the front side with electrical contact to the back side Al metallization; a silicide layer formed by rapid thermal annealing of the plated nickel (Ni) or cobalt (Co); an optional barrier layer electrodeposited on the silicide; a copper (Cu) layer electrodeposited on the silicide/barrier film layer; and a thin protective layer is chemically applied or electrodeposited on top of the Cu layer.

摘要翻译： 包括硅衬底的太阳能电池的栅格堆叠结构，其中硅的正面被磷掺杂以形成n发射极，硅的背面用铝（Al）金属化丝网印刷; 作为抗反射涂层（ARC）的介电层，施加在硅上; 施加在前侧的掩模层以限定电介质层的栅格开口，其中施加蚀刻方法以打开未屏蔽的栅格区域; 施加到前侧的光诱导的镀镍或钴层与后侧Al金属化电接触; 通过镀镍（Ni）或钴（Co）的快速热退火形成的硅化物层; 电沉积在硅化物上的可选阻挡层; 电沉积在硅化物/阻挡膜层上的铜（Cu）层; 并且将薄的保护层化学施加或电沉积在Cu层的顶部上。

公开(公告)号：US20100084656A1

公开(公告)日：2010-04-08

申请号：US12247474

申请日：2008-10-08

申请人： Cyril Cabral, JR. ,  Michael S. Gordon ,  Jeff McMurray ,  Liesl McMurray ,  Cristina Plettner ,  Paul Andrew Ronsheim

发明人： Cyril Cabral, JR. ,  Michael S. Gordon ,  Jeff McMurray ,  Liesl McMurray ,  Cristina Plettner ,  Paul Andrew Ronsheim

IPC分类号： H01L23/58 ,  H01L21/66

CPC分类号： G01T1/00 ,  H01L22/10

摘要： A structure and a method for operating the same. The method includes providing a detecting structure which includes N detectors. N is a positive integer. A fabrication step is simultaneously performed on the detecting structure and M product structures in a fabrication tool resulting in a particle-emitting layer on the detecting structure. The detecting structure is different than the M product structures. The M product structures are identical. M is a positive integer. An impact of emitting particles from the particle-emitting layer on the detecting structure is analyzed after said performing is performed.

摘要翻译： 一种结构及其操作方法。 该方法包括提供包括N个检测器的检测结构。 N是正整数。 在制造工具中的检测结构和M产品结构上同时进行制造步骤，从而在检测结构上产生颗粒发射层。 检测结构与M产品结构不同。 M产品结构相同。 M是正整数。 在执行所述执行之后，分析从颗粒发射层发射颗粒对检测结构的影响。

公开(公告)号：US20090298244A1

公开(公告)日：2009-12-03

申请号：US12537275

申请日：2009-08-07

申请人： Bruce B. Doris ,  Cyril Cabral, JR. ,  Elizabeth A. Duch ,  Stephen M. Rossnagel ,  Michelle L. Steen

发明人： Bruce B. Doris ,  Cyril Cabral, JR. ,  Elizabeth A. Duch ,  Stephen M. Rossnagel ,  Michelle L. Steen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L29/4958 ,  H01L29/7845

摘要： NFET and PFET devices with separately stressed channel regions, and methods of their fabrication is disclosed. A FET is disclosed which includes a gate, which gate includes a metal in a first state of stress. The FET also includes a channel region hosted in a single crystal Si based material, which channel region is overlaid by the gate and is in a second state of stress. The second state of stress of the channel region is of an opposite sign than the first state of stress of the metal included in the gate. The NFET channel is usually in a tensile state of stress, while the PFET channel is usually in a compressive state of stress. The methods of fabrication include the deposition of metal layers by physical vapor deposition (PVD), in such manner that the layers are in stressed states.

摘要翻译： 具有单独应力通道区域的NFET和PFET器件及其制造方法。 公开了一种FET，其包括栅极，该栅极包括处于第一应力状态的金属。 FET还包括托管在单晶Si基材料中的沟道区域，该沟道区域被栅极覆盖并处于第二应力状态。 沟道区域的第二应力状态与包括在栅极中的金属的第一应力状态相反。 NFET通道通常处于应力的拉伸状态，而PFET通道通常处于应力的压缩状态。 制造方法包括通过物理气相沉积（PVD）沉积金属层，使得层处于应力状态。

公开(公告)号：US20090130845A1

公开(公告)日：2009-05-21

申请号：US11942393

申请日：2007-11-19

申请人： Brett Baker-O'Neal ,  Cyril Cabral, JR. ,  Hariklia Deligianni ,  James J. Kelly ,  Min Zheng

发明人： Brett Baker-O'Neal ,  Cyril Cabral, JR. ,  Hariklia Deligianni ,  James J. Kelly ,  Min Zheng

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  C25D3/38 ,  C25D5/34 ,  H01L21/2885 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of depositing copper directly onto a tantalum alloy layer of an on-chip copper interconnect structure, which includes electrodepositing copper from a neutral or basic electrolyte onto a surface of a tantalum alloy layer, in which the tantalum alloy layer is deposited on a substrate of the on-chip copper interconnect structure, and in which the copper nucleates onto the surface of the tantalum alloy layer without use of a seed layer to form a copper conductor.

摘要翻译： 一种将铜直接沉积在片上铜互连结构的钽合金层上的方法，该方法包括将铜从中性或碱性电解质电沉积到钽合金层的表面上，其中钽合金层沉积在基底上 的芯片铜互连结构，并且其中铜不会使用种子层成核形成铜导体的钽合金层的表面。

公开(公告)号：US20090014878A1

公开(公告)日：2009-01-15

申请号：US12130381

申请日：2008-05-30

申请人： Cyril Cabral, JR. ,  Hariklia Deligianni ,  Randolph F. Knarr ,  Sandra G. Malhotra ,  Stephen Rossnagel ,  Xiaoyan Shao ,  Anna Topol ,  Philippe M. Vereecken

发明人： Cyril Cabral, JR. ,  Hariklia Deligianni ,  Randolph F. Knarr ,  Sandra G. Malhotra ,  Stephen Rossnagel ,  Xiaoyan Shao ,  Anna Topol ,  Philippe M. Vereecken

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/485 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.

摘要翻译： 一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的硅化物或锗化物层，例如钴和/或镍; 接触层，其包含位于介电层顶部并且在空腔内并与底部的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。 金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。 当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。 当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。

公开(公告)号：US20130075908A1

公开(公告)日：2013-03-28

申请号：US13246904

申请日：2011-09-28

申请人： Cyril Cabral, JR. ,  Geraud Jean-Michel Dubois ,  Daniel C. Edelstein ,  Takeshi Nogami ,  Daniel P. Sanders

发明人： Cyril Cabral, JR. ,  Geraud Jean-Michel Dubois ,  Daniel C. Edelstein ,  Takeshi Nogami ,  Daniel P. Sanders

IPC分类号： H01L23/482 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.

摘要翻译： 公开了一种用于制造具有增强的性能和可靠性的互连结构的互连结构和方法，通过最小化氧侵入种子层和互连结构的电镀铜层。 形成电介质层中的至少一个开口。 形成设置在电介质层上的牺牲氧化层。 牺牲氧化层使氧侵入种子层和互连结构的电镀铜层最小化。 形成设置在牺牲氧化层上的阻挡金属层。 形成设置在阻挡金属层上的籽晶层。 形成设置在种子层上的电镀铜层。 形成平坦化表面，其中除去部分牺牲氧化层，阻挡金属层，种子层和电镀铜层。 此外，形成设置在平坦化表面上的覆盖层。

公开(公告)号：US20120009771A1

公开(公告)日：2012-01-12

申请号：US12833272

申请日：2010-07-09

申请人： Cyril Cabral, JR. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

发明人： Cyril Cabral, JR. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

IPC分类号： H01L21/3205

CPC分类号： H01L21/28512 ,  H01L21/28518 ,  H01L29/456

摘要： A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.

摘要翻译： 在半导体材料和硅化物层之间的结处形成分离的界面掺杂剂层的方法包括在半导体材料上沉积掺杂的金属层; 退火所述掺杂金属层和所述半导体材料，其中所述退火使所述掺杂金属层的一部分和所述半导体材料的一部分反应以在所述半导体材料上形成所述硅化物层，并且其中所述退火还导致所述分离的界面掺杂剂 层，以形成在半导体材料和硅化物层之间，分离的界面掺杂剂层包含来自掺杂金属层的掺杂剂; 以及从所述硅化物层去除所述掺杂金属层的未反应部分。