公开(公告)号：US08900988B2

公开(公告)日：2014-12-02

申请号：US13088083

申请日：2011-04-15

申请人： Qinghuang Lin ,  Benjamin L. Fletcher ,  Cyril Cabral, Jr.

发明人： Qinghuang Lin ,  Benjamin L. Fletcher ,  Cyril Cabral, Jr.

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L23/5222 ,  H01L21/31127 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/4821 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： Devices and methods for forming a self-aligned airgap interconnect structure includes etching a conductive layer to a substrate to form conductive structures with patterned gaps and filling the gaps with a sacrificial material. The sacrificial material is planarized to expose a top surface of the conductive layer. A permeable cap layer is deposited over the conductive structure and the sacrificial material. Self-aligned airgaps are formed by removing the sacrificial material through the permeable layer.

摘要翻译： 用于形成自对准气隙互连结构的装置和方法包括将导电层蚀刻到衬底以形成具有图案化间隙的导电结构并用牺牲材料填充间隙。 将牺牲材料平坦化以暴露导电层的顶表面。 在导电结构和牺牲材料上沉积可渗透盖层。 通过可渗透层去除牺牲材料形成自对准的气隙。

公开(公告)号：US20120261788A1

公开(公告)日：2012-10-18

申请号：US13088083

申请日：2011-04-15

申请人： Qinghuang Lin ,  Benjamin L. Fletcher ,  Cyril Cabral, JR.

发明人： Qinghuang Lin ,  Benjamin L. Fletcher ,  Cyril Cabral, JR.

IPC分类号： H01L29/06 ,  H01L21/28 ,  H01L21/31

CPC分类号： H01L23/5222 ,  H01L21/31127 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/4821 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： Devices and methods for forming a self-aligned airgap interconnect structure includes etching a conductive layer to a substrate to form conductive structures with patterned gaps and filling the gaps with a sacrificial material. The sacrificial material is planarized to expose a top surface of the conductive layer. A permeable cap layer is deposited over the conductive structure and the sacrificial material. Self-aligned airgaps are formed by removing the sacrificial material through the permeable layer.

摘要翻译： 用于形成自对准气隙互连结构的装置和方法包括将导电层蚀刻到衬底以形成具有图案化间隙的导电结构并用牺牲材料填充间隙。 将牺牲材料平坦化以暴露导电层的顶表面。 在导电结构和牺牲材料上沉积可渗透盖层。 通过可渗透层去除牺牲材料形成自对准的气隙。

公开(公告)号：US09209126B2

公开(公告)日：2015-12-08

申请号：US13606788

申请日：2012-09-07

申请人： Qinghuang Lin ,  Sanjay Mehta ,  Hosadurga Shobha

发明人： Qinghuang Lin ,  Sanjay Mehta ,  Hosadurga Shobha

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5222 ,  H01L21/768 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L23/53295 ,  H01L2221/1026 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a given lithographic technology and the width is formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel. The sidewall portions form spaced-apart openings. Conductive structures fill the spaced-apart openings and are separated by the sidewall portions to form single damascene structures.

摘要翻译： 互连结构及其制造方法包括层间电介质层的侧壁部分。 侧壁部分具有小于给定平版印刷技术的最小特征尺寸的宽度，并且当在心轴的垂直表面上共形形成时，宽度由层间电介质层的厚度形成。 侧壁部分形成间隔开的开口。 导电结构填充间隔开的开口并且被侧壁部分分开以形成单个镶嵌结构。

公开(公告)号：US08637395B2

公开(公告)日：2014-01-28

申请号：US12619298

申请日：2009-11-16

申请人： Maxime Darnon ,  Qinghuang Lin

发明人： Maxime Darnon ,  Qinghuang Lin

IPC分类号： H01L21/4763

CPC分类号： H01L21/76804 ,  C08G77/04 ,  H01L21/02126 ,  H01L21/02318 ,  H01L21/31 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A single damascene or dual damascene interconnect structure fabricated with a photo-patternable low-k dielectric (PPLK) which is cured after etching. This method prevents the PPLK damage and the tapering of the edges of the interconnect structure. In one embodiment, the method of the present invention includes depositing a photo-patternable low-k (PPLK) material atop a substrate. The at least one PPLK material is patterned, creating a single damascene structure. For dual damascene structures, a second PPLK layer is coated and patterned. An etch process is performed to transfer the pattern from the PPLK material into at least a portion of the substrate. A diffusion liner and a conductive material can be deposited after the etch process. The resulting structure is cured anytime after etching in order to transform the resist like PPLK into a permanent low-k material that remains within the structure.

摘要翻译： 用蚀刻后固化的光可图案化低k电介质（PPLK）制造的单镶嵌或双镶嵌互连结构。 该方法防止了PPLK损坏和互连结构边缘的逐渐变细。 在一个实施例中，本发明的方法包括在衬底顶部沉积可光可编码的低k（PPLK）材料。 至少一个PPLK材料被图案化，形成单个镶嵌结构。 对于双镶嵌结构，涂覆和图案化第二PPLK层。 执行蚀刻工艺以将图案从PPLK材料转移到衬底的至少一部分中。 在蚀刻工艺之后可以沉积扩散衬垫和导电材料。 所得到的结构在蚀刻后随时固化，以将抗蚀剂像PPLK转变成保持在结构内的永久低k材料。

公开(公告)号：US08487411B2

公开(公告)日：2013-07-16

申请号：US13407141

申请日：2012-02-28

申请人： Qinghuang Lin

发明人： Qinghuang Lin

IPC分类号： H01L23/58

CPC分类号： H01L21/3105 ,  C08G77/04 ,  G03F7/0035 ,  G03F7/0757 ,  G03F7/091 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/31 ,  H01L21/31144 ,  H01L21/3121

摘要： A double patterned semiconductor structure is provided. The structure includes a first patterned and cured low-k structure located on a first portion of an antireflective coating, and a second patterned and cured low-k structure located on a second portion of the antireflective coating, wherein the second patterned and cured low-k structure is spaced apart from the first patterned and cured low-k dielectric structure.

摘要翻译： 提供双重图案化的半导体结构。 该结构包括位于抗反射涂层的第一部分上的第一图案化和固化的低k结构，以及位于抗反射涂层的第二部分上的第二图案化和固化的低k结构，其中第二图案化和固化的低k结构， k结构与第一图案化和固化的低k电介质结构间隔开。

公开(公告)号：US08476758B2

公开(公告)日：2013-07-02

申请号：US11971470

申请日：2008-01-09

申请人： Qinghuang Lin

发明人： Qinghuang Lin

IPC分类号： H01L23/52

CPC分类号： H01L23/532 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： The present invention provides a method of fabricating an airgap-containing interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene airgap-containing low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating.

摘要翻译： 本发明提供一种制造含气隙的互连结构的方法，其中可图案化的低k材料代替了使用单独的光致抗蚀剂和电介质材料的需要。 具体而言，本发明涉及一种制备具有至少一个可图案化的低k电介质和至少一种无机抗反射涂层的单镶嵌和双镶嵌气隙低k互连结构的简化方法。

公开(公告)号：US08415248B2

公开(公告)日：2013-04-09

申请号：US13474349

申请日：2012-05-17

申请人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Sampath Purushothaman ,  Terry A. Spooner ,  Shawn M. Walsh

发明人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Sampath Purushothaman ,  Terry A. Spooner ,  Shawn M. Walsh

IPC分类号： H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/4846 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L23/49894 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.

摘要翻译： 提供了自对准的互连结构，其包括位于衬底的表面上的第一图案化和固化的低k材料，其中第一图案化和固化的低k材料包括至少一个第一互连图案（通孔或沟槽图案） 其中。 具有不同于第一互连图案的至少一个第二互连图案的第二图案化和固化的低k材料位于第一图案化和固化的低k材料的顶部。 第二图案化和固化的低k材料的一部分部分地填充第一图案化和固化的低k材料内的至少一个第一互连。 导电材料填充至少一个第一互连图案和至少一个第二互连图案。 还提供了形成这种自对准互连结构的方法。

公开(公告)号：US20130009312A1

公开(公告)日：2013-01-10

申请号：US13603017

申请日：2012-09-04

申请人： Maxime Darnon ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Qinghuang Lin

发明人： Maxime Darnon ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Qinghuang Lin

IPC分类号： H01L23/485 ,  H05K1/09 ,  H05K1/02

CPC分类号： H01L23/53295 ,  H01L21/4846 ,  H01L21/76808 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/49894 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure.

摘要翻译： 微电子结构内的互连结构和用于在微电子结构内制造互连结构的方法使用可显影底部抗反射涂层和位于其上的至少一个可成像的层间电介质层，该基底包括基底电介质层和 第一导体层，其位于并形成为嵌入在所述基极介质层内。 使用可显影底部抗反射涂层和至少一个可成像的层间电介质层的事件可以通过至少一个可成像的层间间隔形成孔，例如但不限于双镶嵌孔， 介电层和可显影的抗反射涂层，以在位于和形成在第一导体层上时露出覆盖层，当在微电子结构内形成互连结构时，不使用干等离子体蚀刻方法。

公开(公告)号：US20130001781A1

公开(公告)日：2013-01-03

申请号：US13602126

申请日：2012-09-01

申请人： Maxime Darnon ,  Qinghuang Lin

发明人： Maxime Darnon ,  Qinghuang Lin

IPC分类号： H01L23/532 ,  H01L23/522

CPC分类号： H01L21/76804 ,  C08G77/04 ,  H01L21/02126 ,  H01L21/02318 ,  H01L21/31 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An interconnect structure is provided which includes at least one patterned and cured low-k material located directly on a surface of a substrate; and at least one least one conductively filled region embedded within an interconnect pattern located within the at least one patterned and cured low-k material, wherein the at least one conductively filled region has an inflection point at a lower region of the interconnect pattern that is in proximity to an upper surface of the substrate and the interconnect region having an upper region that has substantially straight sidewalls.

摘要翻译： 提供了一种互连结构，其包括直接位于衬底的表面上的至少一个图案化和固化的低k材料; 以及至少一个导电填充区域，其嵌入位于所述至少一个图案化和固化的低k材料内的互连图案内，其中所述至少一个导电填充区域在所述互连图案的下部区域具有拐点， 靠近衬底的上表面，并且互连区域具有具有基本上直的侧壁的上部区域。

公开(公告)号：US20120325532A1

公开(公告)日：2012-12-27

申请号：US13602496

申请日：2012-09-04

申请人： Qinghuang Lin

发明人： Qinghuang Lin

IPC分类号： H05K1/11 ,  H05K1/09 ,  H05K1/02 ,  H05K1/00

CPC分类号： H01L21/76825 ,  H01L21/0276 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76826 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An interconnect structure is provided that may include at least one cured permanent patterned dielectric material located on a surface of a substrate. The at least one cured permanent patterned dielectric material is a cured product of a patterned photoresist that includes a dielectric enabling element therein. The structure further includes at least one conductively filled region embedded within the at least one cured permanent patterned dielectric material.

摘要翻译： 提供了互连结构，其可以包括位于衬底的表面上的至少一个固化的永久性图案化电介质材料。 所述至少一种固化的永久性图案化电介质材料是在其中包括电介质使能元件的图案化光致抗蚀剂的固化产物。 所述结构还包括至少一个导电填充区域，其嵌入在所述至少一个固化的永久构图电介质材料内。