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21.发明授权Methods for the determination of film continuity and growth modes in thin dielectric films 失效薄介电膜中膜连续性和生长模式的测定方法公开(公告)号：US07459913B2
公开(公告)日：2008-12-02
申请号：US10710947
申请日：2004-08-13
CPC分类号： H01L21/02263 , C23C16/45525 , C23C16/52 , H01L21/0228 , H01L21/314
摘要： A method for determining film continuity and growth modes in thin dielectric films includes: depositing a material on the substrate using a first value of a growth metric; depositing an amount of charge on a surface of the material; repetitively measuring a surface voltage of the material until an onset of tunneling to provide a Vtunnel (or Etunnel) value; repeating the above steps for different values of the growth metric; and comparing the Vtunnel (or Etunnel) values for different values of the growth metric to provide a measure of the continuity of the material on the substrate. The growth modes of the material can be determined by comparing the first derivative of the Vtunnel or Etunnel per growth metric curve versus the growth metric, and examining the linearity of the results of the comparison. The growth metric parameters may include thickness, time, precursor cycles, or temperature.
摘要翻译： 用于确定薄介电膜中的膜连续性和生长模式的方法包括：使用生长度量的第一值将材料沉积在衬底上; 在所述材料的表面上沉积一定量的电荷; 重复地测量材料的表面电压，直到隧道开始，以提供Vtunnel（或Etunnel）值; 对生长度量的不同值重复上述步骤; 以及比较生长度量值的不同值的Vtunnel（或Etunnel）值，以提供衬底上材料的连续性的量度。 材料的生长模式可以通过比较Vtunnel或Etunnel的每个生长度量曲线的一阶导数与生长指标，并检查比较结果的线性来确定。 生长度量参数可以包括厚度，时间，前体循环或温度。
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公开(公告)号：US07186625B2
公开(公告)日：2007-03-06
申请号：US10709768
申请日：2004-05-27
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L23/5223 , H01L23/5227 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A structure, apparatus and method for utilizing vertically interdigitated electrodes serves to increase the capacitor area surface while maintaining a minimal horizontal foot print. Since capacitance is proportional to the surface area the structure enables continual use of current dielectric materials such as Si3N4 at current thicknesses. In a second embodiment of the interdigitated MIMCAP structure the electrodes are formed in a spiral fashion which serves to increase the physical strength of the MIMCAP. Also included is a spiral shaped capacitor electrode which lends itself to modular design by offering a wide range of discrete capacitive values easily specified by the circuit designer.
摘要翻译： 用于利用垂直交错电极的结构，装置和方法用于增加电容器面积，同时保持最小的水平脚印。 由于电容与表面积成比例，因此该结构能够连续使用当前厚度的当前介电材料，例如Si 3 N 4。 在叉指MIMCAP结构的第二实施例中，电极以螺旋方式形成，其用于增加MIMCAP的物理强度。 还包括螺旋形电容器电极，其通过提供电路设计者容易指定的宽范围的离散电容值来适应模块化设计。
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公开(公告)号：US09029959B2
公开(公告)日：2015-05-12
申请号：US13537101
申请日：2012-06-29
申请人： MaryJane Brodsky , Michael P. Chudzik , Min Dai , Joseph F. Shepard, Jr. , Shahab Siddiqui , Yanfeng Wang , Jinping Liu
发明人： MaryJane Brodsky , Michael P. Chudzik , Min Dai , Joseph F. Shepard, Jr. , Shahab Siddiqui , Yanfeng Wang , Jinping Liu
IPC分类号： H01L29/49 , H01L21/02 , H01L21/28 , H01L21/3115 , H01L21/8234 , H01L29/51
CPC分类号： H01L21/02321 , H01L21/28194 , H01L21/3115 , H01L21/823462 , H01L29/513 , H01L29/517
摘要： A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.
摘要翻译： 复合高介电常数（high-k）栅极电介质包括掺杂的高k栅极电介质和未掺杂的高k栅极电介质的堆叠。 可以通过提供第一高k电介质材料层和掺杂剂金属层的堆叠来形成掺杂的高k栅极电介质，并且对叠层进行退火以引起掺杂剂金属扩散到第一高k电介质材料层中。 通过随后沉积第二高k电介质材料层形成未掺杂的高k栅极电介质。 复合高k栅极电介质可以提供增加的栅极 - 漏极氧化物厚度，而不增加反转氧化物厚度。
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24.发明授权Method of manufacturing scaled equivalent oxide thickness gate stacks in semiconductor devices and related design structure 有权在半导体器件中制造尺寸等效的氧化物厚度栅极叠层的方法及相关设计结构公开(公告)号：US09099461B2
公开(公告)日：2015-08-04
申请号：US13490740
申请日：2012-06-07
申请人： Michael P. Chudzik , Min Dai , Jinping Liu , Paul A. Ronsheim , Joseph F. Shepard, Jr. , Shahab Siddiqui
发明人： Michael P. Chudzik , Min Dai , Jinping Liu , Paul A. Ronsheim , Joseph F. Shepard, Jr. , Shahab Siddiqui
CPC分类号： H01L29/513 , H01L21/28185 , H01L21/28202 , H01L22/12 , H01L22/26 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH3); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.
摘要翻译： 公开了一种形成半导体器件的方法。 该方法包括：在基板上形成电介质区域; 在包括氨（NH 3）在内的环境中退火电介质区域; 在退火期间监测所述衬底和所述电介质区域中的至少一个的氮峰; 并根据氮峰的监测来调整环境参数。
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25.发明授权Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric 失效用于同时形成沟槽电容器电介质和沟槽侧壁器件电介质的半导体方法和结构公开(公告)号：US06936512B2
公开(公告)日：2005-08-30
申请号：US10260085
申请日：2002-09-27
申请人： Michael P. Chudzik , Rajarao Jammy , Carl John Radens , Kenneth T. Settlemyer, Jr. , Padraic Shafer , Joseph F. Shepard, Jr.
发明人： Michael P. Chudzik , Rajarao Jammy , Carl John Radens , Kenneth T. Settlemyer, Jr. , Padraic Shafer , Joseph F. Shepard, Jr.
IPC分类号： H01L21/314 , H01L21/316 , H01L21/8242
CPC分类号： H01L29/66181 , H01L21/3144 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L27/10864 , H01L27/10867
摘要： Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar. The top of the isolation collar is then etched back to expose a portion of the single crystal substrate along the sidewall, and then, a node electrode is formed in conductive contact with the exposed sidewall and also in contact with the high-K dielectric in the lower portion, such that the high-K dielectric remains as a trench sidewall dielectric in the upper portion of the sidewall. In a DRAM memory cell structure, the trench sidewall dielectric may then be used as a gate dielectric of a vertical transistor which accesses the trench storage capacitor in the trench.
摘要翻译： 本文公开了一种在同时形成沟槽电容器和沟槽侧壁装置电介质的高K节点电介质的集成方法。 所述方法包括在半导体衬底的单晶层中形成沟槽，以及沿着沟槽侧壁的一部分形成隔离环，其中所述环在所述单晶层中具有位于所述沟槽顶部下方的顶部。 然后，同时，沿着沟槽侧壁形成高K电介质，高K电介质在包括隔离环的上方的沟槽的上部和隔离环的下方的沟槽的下部延伸 。 然后隔离环的顶部被回蚀以沿着侧壁露出单晶衬底的一部分，然后，形成与暴露的侧壁导电接触并且还与高K电介质接触的节点电极 使得高K电介质保留在侧壁的上部中的沟槽侧壁电介质。 在DRAM存储单元结构中，沟槽侧壁电介质可以用作访问沟槽中的沟槽存储电容器的垂直晶体管的栅极电介质。
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公开(公告)号：US20110298089A1
公开(公告)日：2011-12-08
申请号：US12793051
申请日：2010-06-03
CPC分类号： H01L29/66181 , H01L29/945
摘要： An improved trench capacitor and method of fabrication are disclosed. The trench capacitor utilizes a rare-earth oxide layer to reduce depletion effects, thereby improving performance of the trench capacitor.
摘要翻译： 公开了一种改进的沟槽电容器和制造方法。 沟槽电容器利用稀土氧化物层来减少耗尽效应，从而提高沟槽电容器的性能。
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27.发明授权High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof 失效在电介质/硅衬底界面处耐氧化物生长的高k电介质栅极结构及其制造方法公开(公告)号：US08575709B2
公开(公告)日：2013-11-05
申请号：US13556795
申请日：2012-07-24
申请人： Huiming Bu , Michael P. Chudzik , Wei He , William K. Henson , Siddarth A. Krishnan , Unoh Kwon , Naim Moumen , Wesley C. Natzle
发明人： Huiming Bu , Michael P. Chudzik , Wei He , William K. Henson , Siddarth A. Krishnan , Unoh Kwon , Naim Moumen , Wesley C. Natzle
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/28088 , H01L21/2822 , H01L29/4966 , H01L29/51 , H01L29/66575
摘要： Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.
摘要翻译： 用于制造栅电极/高k电介质栅极结构的方法，其具有改善的耐电介质/硅基衬底界面处二氧化硅（氧化物）生长的能力。 在一个实施例中，形成晶体管栅极结构的方法包括：将氮掺入靠近衬底表面的硅基衬底中; 在所述硅基衬底上沉积高k栅极电介质; 以及在高k电介质上沉积栅电极以形成栅极结构。 在一个实施例中，栅电极包含富含钛的氮化钛以抑制氧的扩散。
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28.发明授权公开(公告)号：US08420473B2
公开(公告)日：2013-04-16
申请号：US12960586
申请日：2010-12-06
IPC分类号： H01L21/8238 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823842 , H01L29/165 , H01L29/4966 , H01L29/51 , H01L29/66545 , H01L29/66606 , H01L29/7848
摘要： A method of simultaneously fabricating n-type and p type field effect transistors can include forming a first replacement gate having a first gate metal layer adjacent a gate dielectric layer in a first opening in a dielectric region overlying a first active semiconductor region. A second replacement gate including a second gate metal layer can be formed adjacent a gate dielectric layer in a second opening in a dielectric region overlying a second active semiconductor region. At least portions of the first and second gate metal layers can be stacked in a direction of their thicknesses and separated from each other by at least a barrier metal layer. The NFET resulting from the method can include the first active semiconductor region, the source/drain regions therein and the first replacement gate, and the PFET resulting from the method can include the second active semiconductor region, source/drain regions therein and the second replacement gate.
摘要翻译： 同时制造n型和p型场效应晶体管的方法可以包括在覆盖第一有源半导体区域的电介质区域中的第一开口中形成具有与栅极电介质层相邻的第一栅极金属层的第一替代栅极。 包括第二栅极金属层的第二替代栅极可以在覆盖在第二有源半导体区域上的电介质区域中的第二开口中邻近栅极电介质层形成。 第一和第二栅极金属层的至少一部分可以沿其厚度的方向堆叠并且通过至少阻挡金属层彼此分离。 由该方法产生的NFET可以包括第一有源半导体区域，其中的源极/漏极区域和第一替换栅极，并且由该方法产生的PFET可以包括第二有源半导体区域，其中的源/漏区域和第二替换 门。
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公开(公告)号：US20120187420A1
公开(公告)日：2012-07-26
申请号：US13427963
申请日：2012-03-23
申请人： Zhengwen Li , Michael P. Chudzik , Unoh Kwon , Filippos Papadatos , Andrew H. Simon , Keith Kwong Hon Wong
发明人： Zhengwen Li , Michael P. Chudzik , Unoh Kwon , Filippos Papadatos , Andrew H. Simon , Keith Kwong Hon Wong
CPC分类号： H01L23/485 , H01L21/28088 , H01L21/28202 , H01L21/76283 , H01L21/76877 , H01L21/823842 , H01L21/823871 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.
摘要翻译： 提供了一种电气装置，其在一个实施例中包括具有第一栅极结构的p型半导体器件，该第一栅极结构包括存在于半导体衬底上的栅极电介质，p型功函数金属层，由钛构成的金属层和 铝和由铝构成的金属填充物。 n型半导体器件也存在于半导体衬底上，该半导体衬底包括第二栅极结构，其包括栅极电介质，由钛和铝构成的金属层以及由铝组成的金属填充物。 层间电介质存在于半导体衬底上。 层间电介质包括到p型和n型半导体器件的源区和漏区的互连。 互连由钛和铝构成的金属层和由铝组成的金属填充物构成。 本公开还提供了形成上述结构的方法。
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30.发明申请公开(公告)号：US20100187610A1
公开(公告)日：2010-07-29
申请号：US12359520
申请日：2009-01-26
申请人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
发明人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/4966 , H01L29/517
摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.
摘要翻译： 半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层 第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且 第三金属层，第三金属层设置在第二中间层上。 或者，省略第一金属层。 制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。
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