公开(公告)号：US11791230B2

公开(公告)日：2023-10-17

申请号：US17409281

申请日：2021-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonsung Kim ,  Doohwan Lee ,  Jinseon Park

IPC: H01L23/31 ,  H01L25/13 ,  H01L23/498 ,  H01L23/00 ,  H01L23/552 ,  H01L25/10 ,  H01L23/522 ,  H01L23/13

CPC classification number: H01L23/3128 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/08 ,  H01L2224/08235

Abstract: A method of manufacturing a fan-out semiconductor package includes forming a frame having a through-hole and including one or more wiring layers; forming a semiconductor chip in the through-hole of the frame; forming an encapsulant covering an upper surface of each of the frame and the semiconductor chip, and filling a space between a wall surface of the through-hole of the frame and a side surface of the semiconductor chip; forming a connection structure below each of the frame and the semiconductor chip; forming a first metal pattern layer on an upper surface of the encapsulant; forming an insulating material on the upper surface of the encapsulant and covering the first metal pattern layer; and forming a second metal pattern layer on the insulating material, a first metal via passing through the insulating material, and a second metal via passing through the insulating material and the encapsulant.

公开(公告)号：US11735532B2

公开(公告)日：2023-08-22

申请号：US17664132

申请日：2022-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsung Kim ,  Doohwan Lee ,  Taeho Ko ,  Bongsoo Kim ,  Seokbong Park

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01P3/08 ,  H01P11/00 ,  H01L23/29

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01P3/081 ,  H01P11/003 ,  H01L2221/68372 ,  H01L2223/6627 ,  H01L2224/214 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/19032 ,  H01L2924/19041 ,  H01L2924/19103

Abstract: A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.

公开(公告)号：US20230161937A1

公开(公告)日：2023-05-25

申请号：US17951580

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Somin Cheon ,  Joonsung Kim ,  Jaewan Song ,  Seunghune Yang ,  Sooyong Lee

IPC: G06F30/3323 ,  G03F7/20

CPC classification number: G06F30/3323 ,  G03F7/70433 ,  G03F7/705 ,  G06F2119/18

Abstract: A mask layout design method capable of quickly and effectively designing a crack-resistant mask layout in a full-chip scale, a mask manufacturing method including the mask layout design method, and a mask layout are provided. The mask layout design method includes designing a full-chip layout with respect to a mask; extracting a representative pattern from the full-chip layout; detecting a stress weak point in the representative pattern; verifying the stress weak point by forming a pattern on a wafer; and changing a design rule with respect to the full-chip layout.

公开(公告)号：US20230014037A1

公开(公告)日：2023-01-19

申请号：US17690154

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  Jaeho Kim ,  Joonsung Kim ,  Jiwon Kim ,  Sukkang Sung ,  Sangdon Lee ,  Jong-Min Lee

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/528 ,  G11C16/04

Abstract: A semiconductor device includes an electrode structure including electrodes stacked on a substrate and an insulating pattern on an uppermost electrode of the electrodes, a vertical structure that penetrates the electrode structure and is connected to the substrate, a first insulating layer on the electrode and the vertical structure, a conductive pattern that penetrates the first insulating layer and is connected to the vertical structure, an upper horizontal electrode on the conductive pattern, and an upper semiconductor pattern that penetrates the upper horizontal electrode and is connected to the conductive pattern. The conductive pattern has a first side surface on the vertical structure and a second side surface on the insulating pattern.

公开(公告)号：US11158581B2

公开(公告)日：2021-10-26

申请号：US16679484

申请日：2019-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonsung Kim ,  Doohwan Lee

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/13

Abstract: A semiconductor package may include: a frame having a cavity and including a wiring structure connecting first and second surfaces of the frame to each other; a first connection structure d on the second surface of the frame and including a first redistribution layer connected to the wiring structure; a semiconductor chip on the first connection structure within the cavity and having connection pads connected to the first redistribution layer; an encapsulant encapsulating the semiconductor chip, covering the first surface of the frame, and having an upper surface substantially coplanar with an upper surface of the wiring structure; and a second connection structure including an insulating layer disposed on the upper surfaces of the encapsulant and the wiring structure, a second redistribution layer on the insulating layer, and vias penetrating through the insulating layer and connecting the wiring structure and the second redistribution layer.

公开(公告)号：US20210202397A1

公开(公告)日：2021-07-01

申请号：US17007945

申请日：2020-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsung Kim ,  Doohwan Lee ,  Taeho Ko ,  Bongsoo Kim ,  Seokbong Park

IPC: H01L23/538 ,  H01L23/29 ,  H01L23/31 ,  H01L23/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01P3/08 ,  H01P11/00

Abstract: A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.

公开(公告)号：US20250106083A1

公开(公告)日：2025-03-27

申请号：US18974930

申请日：2024-12-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yangsoo Kwon ,  Joonsung Kim ,  Jinwoo Oh ,  Yongin Choi

IPC: H04L27/26 ,  H04W4/40 ,  H04W72/20 ,  H04W92/10

Abstract: An apparatus and a method for effectively mapping a reference signal for vehicle-to-everything (V2X) communication in a wireless communication system are provided. A transmission terminal performing the V2X communication includes a processor generating sidelink control information (SCI) and a transceiver transmitting the generated SCI to a reception terminal through a physical sidelink control channel (PSCCH) and a physical sidelink shared channel (PSSCH). A decision on whether to allocate a demodulation reference signal (DMRS) of the PSSCH and the PSCCH to the same orthogonal frequency division multiplexing (OFDM) symbol is made based on a number of subchannels and at least one sized thereof.

公开(公告)号：US20240030089A1

公开(公告)日：2024-01-25

申请号：US18475926

申请日：2023-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunseok Cho ,  Minjeong Gu ,  Joonsung Kim ,  Jaehoon Choi

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/552 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4871 ,  H01L21/563 ,  H01L24/16 ,  H01L25/18 ,  H01L25/0655 ,  H01L23/3185 ,  H01L2924/3025 ,  H01L2224/16227 ,  H01L2924/1616 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/30111

Abstract: A method of manufacturing a semiconductor package is provided and includes: forming a lower redistribution structure, the lower redistribution structure including lower redistribution patterns having lower connection pads; forming an upper redistribution structure on a boundary surface of the lower redistribution structure, the upper redistribution structure including upper redistribution patterns having upper connection pads electrically connected to the lower connection pads; forming openings exposing at least a portion of each of the lower connection pads; disposing an interposer substrate, including the lower redistribution structure and the upper redistribution structure, on a base substrate, the lower connection pads of the interposer substrate electrically connected to wiring patterns of the base substrate through lower connection bumps disposed on the openings; and disposing at least one of semiconductor chips, including connection pads, on the interposer substrate, the connection pads electrically connected to the upper connection pads through upper connection bumps.

公开(公告)号：US11854912B2

公开(公告)日：2023-12-26

申请号：US17196538

申请日：2021-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonsung Kim ,  Yonghwan Kwon ,  Sanguk Kim

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L22/32 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/24 ,  H01L2224/022 ,  H01L2224/24226

Abstract: A semiconductor package is provided. The semiconductor package includes a chip pad of a semiconductor chip, the chip pad including a connection portion and a test portion in a first surface of the chip pad; a barrier layer covering the chip pad, the barrier layer defining a first opening and a second opening that is separate from the first opening, the first opening exposing the connection portion of the chip pad, and the second opening exposing the test portion of the chip pad; and a redistribution structure.

公开(公告)号：US20220392843A1

公开(公告)日：2022-12-08

申请号：US17562127

申请日：2021-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonsung Kim

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/34

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate and a first chip pad on a first bottom surface of the first semiconductor substrate, a second semiconductor chip including a second semiconductor substrate and a second chip pad on a second top surface of the second semiconductor substrate, a lower redistribution structure provided under the first semiconductor chip and the second semiconductor chip, the lower redistribution structure including a lower redistribution pattern, the lower redistribution pattern including a first lower redistribution via pattern contacting the first chip pad, a molding layer covering the first semiconductor chip and the second semiconductor chip, an upper redistribution structure including an upper redistribution pattern, the upper redistribution pattern including a first upper redistribution via pattern connected to the second chip pad, and a conductive connection structure electrically connecting the lower redistribution pattern to the upper redistribution pattern.