公开(公告)号：US20200013714A1

公开(公告)日：2020-01-09

申请号：US16168232

申请日：2018-10-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luisa Lin ,  Mohan Dunga ,  Venkatesh P. Ramachandra ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L27/11582 ,  H01L49/02

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.

公开(公告)号：US20200013434A1

公开(公告)日：2020-01-09

申请号：US16168168

申请日：2018-10-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luisa Lin ,  Mohan Dunga ,  Venkatesh P. Ramachandra ,  Peter Rabkin ,  Masaaki Higashitani

IPC: G11C5/06 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  G11C5/10 ,  G11C16/28 ,  G11C16/24 ,  G11C16/08

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the I/O pads.

公开(公告)号：US09935050B2

公开(公告)日：2018-04-03

申请号：US15634423

申请日：2017-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mohan Dunga ,  Yuki Mizutani ,  Zhenyu Lu

IPC: H01L29/06 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/24 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/66666 ,  H01L29/7883 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

Abstract: A multi-tier memory device includes a first tier structure overlying a substrate and containing a first alternating stack of first insulating layers and first electrically conductive layers, and first memory stack structures each including a first memory film and a first vertical semiconductor channel, a source line overlying the first tier structure, and a second tier structure overlying the source line and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory stack structures each including a second memory film and a second vertical semiconductor channel.

公开(公告)号：US20170358365A1

公开(公告)日：2017-12-14

申请号：US15181346

申请日：2016-06-13

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Gerrit Jan Hemink ,  Mohan Dunga ,  Bijesh Rajamohanan ,  Changyuan Chen

IPC: G11C16/28 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C16/28 ,  G06F11/1068 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/1204

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.

公开(公告)号：US20200294910A1

公开(公告)日：2020-09-17

申请号：US16886702

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luisa Lin ,  Mohan Dunga ,  Venkatesh P. Ramachandra ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L27/11582

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.

公开(公告)号：US10559370B2

公开(公告)日：2020-02-11

申请号：US15928976

申请日：2018-03-22

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Piyush Dak ,  Wei Zhao ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Mohan Dunga

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10 ,  G11C16/24 ,  G11C11/56 ,  G11C16/04

Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programming operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.

公开(公告)号：US20200013795A1

公开(公告)日：2020-01-09

申请号：US16141149

申请日：2018-09-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mohan Dunga ,  James Kai ,  Venkatesh P. Ramachandra ,  Piyush Dak ,  Luisa Lin ,  Masaaki Higashitani

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  G11C16/10 ,  G11C16/28 ,  G11C7/10

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.

公开(公告)号：US20190295669A1

公开(公告)日：2019-09-26

申请号：US15928976

申请日：2018-03-22

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Piyush Dak ,  Wei Zhao ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Mohan Dunga

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10

Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programing operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.

公开(公告)号：US10304551B2

公开(公告)日：2019-05-28

申请号：US15194295

申请日：2016-06-27

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Mohan Dunga ,  Gerrit Jan Hemink ,  Changyuan Chen

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for erase depth control. One apparatus includes a block of non-volatile storage cells. A controller is configured to perform a first erase operation on a block of non-volatile storage cells. A controller for a block is configured to determine a first set of storage cells of the block having a faster erase speed than a second set of storage cells of the block based on a verify voltage threshold. A controller for a block is configured to perform a second erase operation on the block using different voltages for a first set of storage cells and a second set of storage cells of the block.

公开(公告)号：US10115459B1

公开(公告)日：2018-10-30

申请号：US15720556

申请日：2017-09-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Katsuo Yamada ,  Tomoyasu Kakegawa ,  Peter Rabkin ,  Jayavel Pachamuthu ,  Mohan Dunga ,  Masaaki Higashitani

IPC: G11C16/06 ,  G11C13/00 ,  H01B7/00 ,  H01B1/02 ,  B23P19/04 ,  B05D1/26 ,  H01B3/16

Abstract: An opening is formed through at least one dielectric material layer. A first metallic liner is formed on a bottom surface and sidewalls of the opening by depositing a first metallic material. A metal portion including an elemental metal or an intermetallic alloy of at least two elemental metals is formed on the first metallic liner. A second metallic liner including a second metallic material is formed directly on a top surface of the metal portion. The first metallic material and the second metallic material differ in composition. The first metallic liner and the second metallic liner contact an entirety of all surfaces of the metal portion. The first and second metallic liners can protect the metal portion from a subsequently deposited dielectric material layer, which may be formed as an air-gap dielectric layer after recessing the at least one dielectric material layer.