公开(公告)号：US10726921B2

公开(公告)日：2020-07-28

申请号：US15942044

申请日：2018-03-30

Applicant: SanDisk Technologies LLC

Inventor： Chia-Lin Hsiung ,  Fumiaki Toyama ,  Tai-Yuan Tseng ,  Yan Li

IPC: G11C11/34 ,  G11C16/08 ,  H01L27/11556 ,  H01L23/528 ,  G11C16/04 ,  H01L27/11582 ,  G11C11/56

Abstract: A three-dimensional block includes a stack comprising a plurality of control gate layers configured to bias memory cells of the block. The block includes a plurality of track regions that includes three or more hookup regions. The plurality of track regions separate the memory cells into three memory cell regions. Tracks extending in the track regions supply voltages to the hookup regions. A system includes a memory plane of blocks, and a plurality of track regions, each extending across the memory plane of blocks.

公开(公告)号：US20200227125A1

公开(公告)日：2020-07-16

申请号：US16829692

申请日：2020-03-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Gerrit Jan Hemink ,  Tai-Yuan Tseng ,  Yan Li

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/04 ,  G11C11/56

Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.

公开(公告)号：US20190179573A1

公开(公告)日：2019-06-13

申请号：US15994116

申请日：2018-05-31

Applicant: SanDisk Technologies LLC

Inventor： Chi-Lin Hsu ,  Tai-Yuan Tseng ,  Yan Li ,  Hiroyuki Mizukoshi

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G11C29/16 ,  G11C11/00 ,  G11C5/06 ,  G11C11/4072 ,  G06F8/65

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.

公开(公告)号：US20190179532A1

公开(公告)日：2019-06-13

申请号：US16003515

申请日：2018-06-08

Applicant: SANDISK TECHNOLOGIES LLC?

Inventor： Tai-Yuan Tseng ,  Hiroyuki Mizukoshi ,  Chi-Lin Hsu ,  Yan Li

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26

Abstract: An apparatus includes a first processor that generates first control signals to control a first circuit to perform memory operations on memory cells. A first number of first physical signal lines delivers the first control signals to a conversion circuit. A second number of second physical signal lines delivers converted control signals to the first circuit. The conversion circuit is coupled by the first number of first physical signal lines to the first processor and by the second number of second physical signal lines to the first circuit. The conversion circuit converts the first control signals to the converted control signals, and outputs the converted control signals to the first circuit. The first number of first physical signal lines is less than the second number of second physical signal lines to reduce the first number of first physical signal lines coupled between the first processor and the first circuit.

公开(公告)号：US20180374518A1

公开(公告)日：2018-12-27

申请号：US15630079

申请日：2017-06-22

Applicant: SanDisk Technologies LLC

Inventor： Tai-Yuan Tseng ,  Anirudh Amarnath

IPC: G11C7/08 ,  G11C11/16 ,  G11C13/00

CPC classification number: G11C7/08 ,  G11C7/12 ,  G11C11/1673 ,  G11C11/5628 ,  G11C11/5642 ,  G11C13/004 ,  G11C13/0064 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2013/0042 ,  G11C2213/71

Abstract: A sense circuit is provided in which the threshold voltage of a memory cell is sensed relative to two different levels using a single control gate voltage on the memory cell. These two levels can be lower and higher verify voltages of a data state in a programming operation, or two read levels of a read operation. A sense node is charged up to a peak level by a pre-charge voltage and by capacitive coupling. The sense node then discharges into the bit line. The sense node voltage is decreased first and second times by capacitive coupling after which first and second bits of data are output based on a level of the sense node. The first and second bits indicate a level of the sense node relative to the lower and higher verify voltages, respectively.

公开(公告)号：US10115440B2

公开(公告)日：2018-10-30

申请号：US15625848

申请日：2017-06-16

Applicant: SanDisk Technologies LLC

Inventor： Qui Nguyen ,  Alexander Chu ,  Kenneth Louie ,  Anirudh Amarnath ,  Jixin Yu ,  Yen-Lung Jason Li ,  Tai-Yuan Tseng ,  Jong Yuh

IPC: G11C8/08 ,  G11C5/06 ,  H01L27/112 ,  G11C8/10 ,  G06F13/40

Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.

公开(公告)号：US09754645B2

公开(公告)日：2017-09-05

申请号：US14924498

申请日：2015-10-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Anirudh Amarnath ,  Tai-Yuan Tseng

IPC: G11C7/00 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C7/02 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24

Abstract: An apparatus includes a first bit line coupled to a first storage element and a second bit line coupled to a second storage element. A first bit line charging circuit is coupled to the first bit line and is configured to charge the first bit line to a first bias voltage of multiple bias voltages based on a first programming state. A second bit line charging circuit is coupled to the second bit line and is configured to charge the second bit line to a second bias voltage of the multiple bias voltages based on a second programming state. The second programming state is different than the first programming state.

公开(公告)号：US11901018B2

公开(公告)日：2024-02-13

申请号：US17562123

申请日：2021-12-27

Applicant: SanDisk Technologies LLC

Inventor： Iris Lu ,  Tai-Yuan Tseng ,  Chia-Kai Chou

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/24 ,  G11C16/34 ,  G11C11/16 ,  H01L25/065

CPC classification number: G11C16/26 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1677 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3459 ,  H01L25/0657 ,  H01L2225/06562

Abstract: A local data bus of a sense amplifier associated with one bit line is used to perform logical operations for a sensing operation performed by another sense amplifier associated with a different bit line. Each sense amplifier circuit includes a sensing node that is pre-charged, then discharged through a selected memory cell and a local data bus with a number of data latches connected. Target program data can be stored in the latches and combined in logical combinations with the sensed value of the memory cell to determine whether it has verified. By including a transfer circuit between the local data buses of a pair of sense amplifiers, the logical operations of a first sense amplifier can be performed using the local data bus of the paired sense amplifier, freeing the first sense amplifier's sense node to be concurrently pre-charged for a subsequent sensing operation, thereby improving performance.

公开(公告)号：US11875842B2

公开(公告)日：2024-01-16

申请号：US17522414

申请日：2021-11-09

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Deepanshu Dutta ,  Tai-Yuan Tseng

IPC: G11C7/12 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/4076

CPC classification number: G11C11/4096 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087

Abstract: A memory device with one or more planes having sub-blocks is disclosed. The memory device may further include a voltage switch transistor for each of sub-blocks. Additionally, the memory device may further include a row decoder for each of sub-blocks. As a result, an operation to two sub-blocks can be performed at different times. For example, using a row decoder and voltage switch transistor, a sub-block can be initially read, followed by a subsequent read of another sub-block using a separate row decoder and voltage switch transistor. By staggering the read operations through a time delay, the peak current Icc associated with the supply voltage can be reduced.

公开(公告)号：US11798631B2

公开(公告)日：2023-10-24

申请号：US17507606

申请日：2021-10-21

Applicant: SanDisk Technologies LLC

Inventor： Iris Lu ,  Tai-Yuan Tseng

IPC: G11C16/24 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/26

Abstract: Read and write circuitry, described herein, comprises data latches, each data latch connected to a bit line and arranged in a same column as the bit line; and transfer latches, each transfer latch connected to a data latch and arranged in a same column as the data latch. Further, circuitry described herein is configured to: transfer a word to and from the transfer latches of a first column and the subset of transfer latches of a second column; transfer a first portion of the word between the transfer latches of the first column and data latches of the first column that are connected to the transfer latches of the first column; and transfer a second portion of the word between the subset of transfer latches and data latches of the second column that are connected to the subset of transfer latches.