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    Systems and methods for soft data utilization in a solid state memory system
    26.
    发明授权
    Systems and methods for soft data utilization in a solid state memory system 有权
    在固态存储器系统中软数据利用的系统和方法

    公开(公告)号：US09575832B2

    公开(公告)日：2017-02-21

    申请号：US14956162

    申请日：2015-12-01

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Yunxiang Wu ,  Yu Cai ,  Erich F. Haratsch

    IPC: H03M13/00 ,  G06F11/10 ,  H03M13/45

    CPC classification number: H03M13/1111 ,  G06F11/1008 ,  G06F11/1012 ,  G06F11/1068 ,  H03M13/45 ,  H03M13/611

    Abstract: Systems and methods relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. An example data processing system includes a first circuit operable to yield a modified soft data set from a data set accessed from a solid state memory device, and a second circuit operable to apply a data decoding algorithm to the modified soft data to yield a decoded output.

    Abstract translation: 一般涉及固态存储器的系统和方法，更具体地涉及用于从固态存储器恢复数据的系统和方法。 示例数据处理系统包括第一电路，其可操作以从从固态存储器件访问的数据集产生修改的软数据集，以及第二电路，可操作以将数据解码算法应用于修改的软数据，以产生解码输出 。

    SYSTEMS AND METHODS FOR LAST WRITTEN PAGE HANDLING IN A MEMORY DEVICE
    27.
    发明申请
    SYSTEMS AND METHODS FOR LAST WRITTEN PAGE HANDLING IN A MEMORY DEVICE 审中-公开
    用于在存储器件中进行书写处理的系统和方法

    公开(公告)号：US20160378598A1

    公开(公告)日：2016-12-29

    申请号：US15195900

    申请日：2016-06-28

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Zhengang Chen ,  Yu Cai ,  Erich F. Haratsch ,  Zhimin Dong

    IPC: G06F11/10 ,  H03M13/37 ,  G11C29/52 ,  G11C16/28 ,  G11C11/56

    CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/28 ,  G11C29/52 ,  G11C2211/5634 ,  G11C2211/5641 ,  H03M13/37

    Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. In one embodiment, the systems and methods include providing a flash memory circuit including a superset of memory cells, accessing a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells, and based at least in part on determining that the group of memory cells was a last written group of memory cells, re-accessing a data set from the group of memory cells using a last written reference value to distinguish bit values in the group of memory cells.

    Abstract translation: 一般涉及固态存储器的系统和方法，更具体地涉及用于从固态存储器恢复数据的系统和方法。 在一个实施例中，系统和方法包括提供包括存储器单元的超集的快闪存储器电路，使用标准参考值从一组存储器单元访问数据集，以区分存储器单元组中的位值，并且基于 至少部分地在于确定存储器单元组是最后写入的存储器单元组，使用最后写入的参考值从存储器单元组重新访问数据组以区分存储器单元组中的位值。

    ERROR CORRECTION CODE (ECC) SELECTION USING PROBABILITY DENSITY FUNCTIONS OF ERROR CORRECTION CAPABILITY IN STORAGE CONTROLLERS WITH MULTIPLE ERROR CORRECTION CODES
    28.
    发明申请
    ERROR CORRECTION CODE (ECC) SELECTION USING PROBABILITY DENSITY FUNCTIONS OF ERROR CORRECTION CAPABILITY IN STORAGE CONTROLLERS WITH MULTIPLE ERROR CORRECTION CODES 审中-公开
    错误校正码（ECC）选择使用具有多个错误校正码的存储控制器中的错误校正能力的可靠性密度函数

    公开(公告)号：US20160315635A1

    公开(公告)日：2016-10-27

    申请号：US15198533

    申请日：2016-06-30

    Applicant: Seagate Technology LLC

    Inventor： Yu Cai ,  Yunxiang Wu ,  Erich F. Haratsch

    IPC: H03M13/11 ,  H03M13/00

    CPC classification number: H03M13/1157 ,  G06F11/1004 ,  G06F11/1048 ,  G06F11/108 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/1174 ,  H03M13/35 ,  H03M13/353 ,  H03M13/356 ,  H03M13/3715 ,  H03M13/611 ,  H03M13/6513 ,  H03M13/6516

    Abstract: A method of characterizing a distribution of a maximum number of errors that first cause uncorrectable error correction code failure for hard low density parity check codes includes selecting a low density parity check code, generating encoded data with the low density parity check code and writing the encoded data to a number of memory blocks, reading the encoded data from the number of memory blocks and determining any pages having a first uncorrectable error correction code failure, determining a number of raw bit errors for each page having a first uncorrectable error correction code failure, incrementing an error count value corresponding to each of the numbers of raw bit errors determined, and repeating the generating, reading, determining, and incrementing steps for a predetermined range of values of a predetermined reliability statistic of the memory blocks.

    Abstract translation: 表征最初数量的错误的分配的方法，其首先导致用于硬质低密度奇偶校验码的不可纠正的纠错码失败包括选择低密度奇偶校验码，用低密度奇偶校验码生成编码数据，并将编码的 数据到多个存储器块，从存储器块的数量读取编码数据并确定具有第一不可校正错误校正码故障的任何页面，确定具有第一不可校正错误校正码故障的每个页面的原始位错误的数量， 增加与所确定的原始比特错误数量对应的错误计数值，并重复对存储块的预定可靠性统计量的预定范围的值的生成，读取，确定和递增步骤。

    Interleaving codewords over multiple flash planes
    29.
    发明授权
    Interleaving codewords over multiple flash planes 有权
    在多个闪存平面上交织码字

    公开(公告)号：US09405480B2

    公开(公告)日：2016-08-02

    申请号：US14156693

    申请日：2014-01-16

    Applicant: Seagate Technology LLC

    Inventor： Ning Chen ,  Yu Cai ,  Yunxiang Wu

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0688

    Abstract: An apparatus having an interface to a plurality of memories and a circuit is disclosed. Each memory generally has a plurality of planes and is nonvolatile. The circuit is configured to (i) generate a plurality of codewords by encoding a plurality of data units, (ii) generate a plurality of slices by parsing the codewords, (iii) generate a plurality of pages by interleaving the slices and (iv) write the pages in parallel into respective ones of the planes.

    Abstract translation: 公开了一种具有与多个存储器和电路的接口的装置。 每个存储器通常具有多个平面并且是非易失性的。 电路被配置为（i）通过对多个数据单元进行编码来生成多个码字，（ii）通过解析码字来产生多个片，（iii）通过交错片生成多个页，以及（iv） 将页面并行写入相应的平面中。

    SYSTEMS AND METHODS FOR SOFT DATA UTILIZATION IN A SOLID STATE MEMORY SYSTEM
    30.
    发明申请
    SYSTEMS AND METHODS FOR SOFT DATA UTILIZATION IN A SOLID STATE MEMORY SYSTEM 审中-公开
    在固态存储器系统中软件数据利用的系统和方法

    公开(公告)号：US20160085623A1

    公开(公告)日：2016-03-24

    申请号：US14956162

    申请日：2015-12-01

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Yunxiang Wu ,  Yu Cai ,  Erich F. Haratsch

    IPC: G06F11/10 ,  H03M13/45

    CPC classification number: H03M13/1111 ,  G06F11/1008 ,  G06F11/1012 ,  G06F11/1068 ,  H03M13/45 ,  H03M13/611

    Abstract: Systems and methods relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. An example data processing system includes a first circuit operable to yield a modified soft data set from a data set accessed from a solid state memory device, and a second circuit operable to apply a data decoding algorithm to the modified soft data to yield a decoded output.

    Abstract translation: 一般涉及固态存储器的系统和方法，更具体地涉及用于从固态存储器恢复数据的系统和方法。 示例性数据处理系统包括第一电路，其可操作以从从固态存储器件访问的数据集中产生修改的软数据集，以及第二电路，可操作以将数据解码算法应用于修改的软数据，以产生解码输出 。

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