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    OUTPUT CONTROL CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
    24.
    发明申请
    OUTPUT CONTROL CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME 有权

    公开(公告)号：US20210117349A1

    公开(公告)日：2021-04-22

    申请号：US16855566

    申请日：2020-04-22

    Applicant: SK hynix Inc.

    Inventor： Kyu Young KIM ,  Dae Han KWON ,  Ha Jun JEONG

    IPC: G06F13/20 ,  G11C7/10 ,  G11C7/22

    Abstract: A semiconductor apparatus may include a data output path connected to a data input/output pad and configured to output read data according to a read command, and at least one circuit configuration included in the data output path may perform a pre-toggling operation of toggling its own output signal at least once in an interval between a time point at which the read command has been generated and a time point at which the read data is outputted through the data output path.

    PHASE MIXING CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
    26.
    发明申请
    PHASE MIXING CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME 有权
    相混合电路和包括它们的半导体装置和半导体系统

    公开(公告)号：US20150054558A1

    公开(公告)日：2015-02-26

    申请号：US14092251

    申请日：2013-11-27

    Applicant: SK hynix Inc.

    Inventor： Jae Min JANG ,  Yong Ju KIM ,  Dae Han KWON ,  Kil Ho CHA

    IPC: H03K5/13

    CPC classification number: H03K5/131

    Abstract: A phase mixing circuit includes a first mixing unit configured to mix phases of first and second clocks at a predetermined ratio, and generate a first mixed signal; a second mixing unit configured to mix phases of an inverted signal of the first clock and an inverted signal of the second clock at the predetermined ratio, and generate a second mixed signal; and an output unit configured to generate an output signal based on of the first and second mixed signals.

    Abstract translation: 相位混合电路包括：第一混合单元，被配置为以预定比率混合第一和第二时钟的相位，并产生第一混合信号; 第二混合单元，被配置为以预定比率混合第一时钟的反相信号的相位和第二时钟的反相信号，并产生第二混合信号; 以及输出单元，被配置为基于第一和第二混合信号产生输出信号。

    CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
    27.
    发明申请
    CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME 有权
    时钟发生电路和半导体器件包括它们

    公开(公告)号：US20140002149A1

    公开(公告)日：2014-01-02

    申请号：US13711692

    申请日：2012-12-12

    Applicant: SK HYNIX INC.

    Inventor： Jae Min JANG ,  Yong Ju KIM ,  Dae Han KWON ,  Hae Rang CHOI

    IPC: H03H11/26 ,  H03L7/06

    CPC classification number: H03H11/265 ,  H03L7/06 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/085

    Abstract: A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information.

    Abstract translation: 时钟生成电路包括延迟线，延迟建模块，相位检测块，多更新信号生成块和延迟线。 延迟线延迟输入时钟并产生延迟时钟。 延迟建模块通过建模延迟值将延迟时钟延迟并产生反馈时钟。 相位检测块比较输入时钟和反馈时钟的相位，并产生相位信息，并量化输入时钟和反馈时钟之间的相位差，并产生相位代码。 多更新信号生成块响应于相位代码生成多更新信号。 响应于多更新信号和相位信息，延迟线控制块改变延迟线的延迟量。

    CLOCK DISTRIBUTION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE CLOCK DISTRIBUTION CIRCUIT
    29.
    发明申请
    CLOCK DISTRIBUTION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE CLOCK DISTRIBUTION CIRCUIT 审中-公开

    公开(公告)号：US20200293082A1

    公开(公告)日：2020-09-17

    申请号：US16890717

    申请日：2020-06-02

    Applicant: SK hynix Inc.

    Inventor： Soo Young JANG ,  Dae Han KWON ,  Geun Il LEE ,  Kyu Dong HWANG

    IPC: G06F1/10 ,  H03L7/189 ,  H03K19/0185

    Abstract: A clock distribution circuit may include a data clock generation circuit configured to be input a power source voltage and configured to generate an internal clock signal according to an external clock signal; and a global distribution circuit includes a first circuit and a second circuit coupled to a global line, configured to be input a power source voltage and configured to receive the internal clock signal through the first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through the second circuit, wherein a first bias voltage provided to the first circuit and a second bias voltage provided to the second circuit are controlled independently of each other.

    AMPLIFIER, AND RECEIVING CIRCUIT, SEMICONDUCTOR APPARATUS, AND SYSTEM USING THE AMPLIFIER
    30.
    发明申请
    AMPLIFIER, AND RECEIVING CIRCUIT, SEMICONDUCTOR APPARATUS, AND SYSTEM USING THE AMPLIFIER 审中-公开

    公开(公告)号：US20190356289A1

    公开(公告)日：2019-11-21

    申请号：US16209650

    申请日：2018-12-04

    Applicant: SK hynix Inc.

    Inventor： Sun Ki CHO ,  Dae Han KWON

    IPC: H03F3/45 ,  H03F3/72 ,  H04L25/02

    Abstract: A receiving circuit may include an amplifier. The amplifier may include a first amplification circuit and a second amplification circuit. The first amplification circuit may be configured to differentially amplify a first input signal and a reference signal and configured to generate output signals. The second amplification circuit may be configured to differentially amplify a second input signal and the reference signal and configured to generate the output signals.

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