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    MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME
    21.
    发明申请
    MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME 审中-公开

    公开(公告)号：US20190287625A1

    公开(公告)日：2019-09-19

    申请号：US16168380

    申请日：2018-10-23

    Applicant: SK hynix Inc.

    Inventor： Ji Man HONG ,  Tae Hoon KIM

    IPC: G11C16/16 ,  G11C16/08 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

    Abstract: Provided herein may be a memory device and a memory system including the memory device. The memory device may include a memory block including a plurality of memory cells, a peripheral circuit configured to perform a selective erase operation on the memory cells, and control logic configured to control, during the selective erase operation, the peripheral circuit to apply an erase allowable voltage to a selected word line among a plurality of word lines in the memory block, apply an erase voltage to a selected string among a plurality of strings in the memory block, and float unselected word lines and unselected strings.

    MEMORY SYSTEM INCLUDING SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
    23.
    发明申请
    MEMORY SYSTEM INCLUDING SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
    包括半导体存储器件的存储器系统及其操作方法

    公开(公告)号：US20170025177A1

    公开(公告)日：2017-01-26

    申请号：US14990272

    申请日：2016-01-07

    Applicant: SK hynix Inc.

    Inventor： Tae Hoon KIM

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C7/14 ,  G11C11/1675 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/26 ,  G11C16/3427 ,  G11C2013/0085 ,  G11C2216/14

    Abstract: An operating method of a memory system including first and second one half pages includes acquiring first and second partial data from main data; performing a first program operation to the first one half page of a selected page with the first partial data; and performing a second program operation to the second one half page of the selected page with the second partial data. The first and second partial data may be programmed in the same first column region in the first and second one half pages, respectively.

    Abstract translation: 包括第一和第二半页的存储器系统的操作方法包括从主数据获取第一和第二部分数据; 使用所述第一部分数据对所选择的页面的所述第一页面执行第一编程操作; 以及使用所述第二部分数据对所选择的页面的所述第二半页执行第二程序操作。 第一和第二部分数据可以分别编程在第一和第二半页中的相同的第一列区域中。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    24.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
    半导体存储器件及其操作方法

    公开(公告)号：US20160329105A1

    公开(公告)日：2016-11-10

    申请号：US15211779

    申请日：2016-07-15

    Applicant: SK hynix Inc.

    Inventor： Tae Hoon KIM

    IPC: G11C16/26 ,  G11C16/24 ,  G11C29/50

    CPC classification number: G11C29/50004 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2029/5004

    Abstract: A semiconductor memory device includes memory cells coupled to a word line; and a peripheral circuit configured to read first to kth page data from the memory cells by sequentially applying first to kth test voltages to the word line, where k is a natural number greater than 3, wherein the peripheral circuit is configured to gradually reduce times during which the first to kth test voltages are applied to the word line.

    Abstract translation: 半导体存储器件包括耦合到字线的存储器单元; 以及周边电路，被配置为通过对字线顺序地施加第一至第k测试电压来从存储器单元读取第一至第k页数据，其中k是大于3的自然数，其中外围电路被配置为逐渐减少 将第一至第k个测试电压施加到字线。

    DATA STORAGE DEVICE AND METHOD OF PROGRAMMING MEMORY CELLS
    26.
    发明申请
    DATA STORAGE DEVICE AND METHOD OF PROGRAMMING MEMORY CELLS 有权
    数据存储设备和编程存储器单元的方法

    公开(公告)号：US20160148695A1

    公开(公告)日：2016-05-26

    申请号：US14947567

    申请日：2015-11-20

    Applicant: SK hynix Inc.

    Inventor： Tae Hoon KIM

    IPC: G11C16/12 ,  G11C11/56 ,  G11C29/04 ,  G11C16/34

    CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2211/5621 ,  G11C2211/5644

    Abstract: A method of programming a non-volatile memory device includes programming memory cells selected from the plurality of memory cells by increasing turn values of program loops based on an incremental step pulse program (ISPP) algorithm; detecting a first turn value of a first program loop wherein, in the first program loop, a first number or a first ratio of first unprogrammed memory cells is smaller than or equal to a first set value; calculating a second turn value of a second program loop based on the first turn value wherein, in the second program loop, a second number or a second ratio of second unprogrammed memory cells is expected to be smaller than or equal to a second set value, the second set value being smaller than the first set value; executing subsequent program loops on the unprogrammed memory cells up to the second program loop; detecting a third number or a third ratio of third unprogrammed memory cells in the second program loop; comparing the third number or the third ratio of the third unprogrammed memory cells to the second set value; determining a program pass when the third number or the third ratio of the third unprogrammed memory cells is smaller than or equal to the second set value; and determining a program fail when the third number or the third ratio of the unprogrammed memory cell exceeds the second set value.

    Abstract translation: 一种编程非易失性存储器件的方法包括：通过基于增量步进脉冲程序（ISPP）算法增加程序循环的转向量来编程从多个存储器单元中选择的存储器单元; 检测第一程序循环的第一转弯值，其中在第一程序循环中，第一未编程存储单元的第一数量或第一比率小于或等于第一设定值; 基于第一匝值计算第二程序循环的第二匝数值，其中在第二程序循环中第二未编程存储器单元的第二数量或第二比率预期小于或等于第二设定值， 所述第二设定值小于所述第一设定值; 在未编程的存储器单元上执行直到第二程序循环的后续程序循环; 检测所述第二程序循环中的第三未编程存储器单元的第三数量或第三比率; 将第三未编程存储单元的第三数量或第三比率与第二设定值进行比较; 当所述第三未编程存储器单元的第三数量或第三比率小于或等于所述第二设定值时，确定程序通过; 并且当所述未编程的存储单元的第三数量或所述第三比率超过所述第二设定值时，确定程序失败。

    DATA STORAGE SYSTEM AND METHOD OF OPERATING THE SAME
    27.
    发明申请
    DATA STORAGE SYSTEM AND METHOD OF OPERATING THE SAME 有权
    数据存储系统及其操作方法

    公开(公告)号：US20150070996A1

    公开(公告)日：2015-03-12

    申请号：US14163762

    申请日：2014-01-24

    Applicant: SK hynix Inc.

    Inventor： Tae Hoon KIM

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/22

    Abstract: A data storage system and a method of operating the same are provided. The method includes performing a program operation on a first page of the pages of a memory block, deciding, when power is switched on after a sudden power-off is generated while the program operation is performed, whether to skip the program operation on a first erase page of the pages based on a second page on which the program operation is performed subsequent to the first page, and performing the program operation on the second page.

    Abstract translation: 提供了一种数据存储系统及其操作方法。 该方法包括在存储器块的页面的第一页上执行编程操作，决定在执行程序操作时在产生突然断电后何时接通电源时，是否首先跳过程序操作 基于在第一页之后执行程序操作的第二页，擦除页面的页面，并且在第二页面上执行程序操作。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    28.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
    半导体存储器件及其操作方法

    公开(公告)号：US20140380109A1

    公开(公告)日：2014-12-25

    申请号：US14292299

    申请日：2014-05-30

    Applicant: SK hynix Inc.

    Inventor： Tae Hoon KIM

    IPC: G11C29/50

    CPC classification number: G11C29/50004 ,  G11C11/5642 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C29/12005 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G11C2029/5004

    Abstract: A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes detecting a first group of changed bits between first and second page data, by comparing the first and second page data, which are read out using first and second test voltages from the memory cells, respectively, detecting a second group of changed bits between the second page data and a third page data, by comparing the second page data with the third page data read out from the memory cells using a third test voltage, comparing the numbers of the first and second groups of changed bits, and determining one of the first to third test voltages as a read voltage according to the comparing of the numbers of the first and second groups of changed bits.

    Abstract translation: 提供一种半导体存储器件及其操作方法。 操作半导体存储器件的方法包括通过比较分别使用来自存储器单元的第一和第二测试电压读出的第一和第二页数据来检测第一和第二页数据之间的第一组改变位，检测 通过使用第三测试电压比较第二页面数据和从存储器单元读出的第三页面数据，比较第一和第二组数据的第二组数据， 根据第一组和第二组改变的比特的数量的比较，将第一至第三测试电压之一确定为读取电压。

    SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    29.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230240086A1

    公开(公告)日：2023-07-27

    申请号：US17857938

    申请日：2022-07-05

    Applicant: SK hynix Inc.

    Inventor： Si Jung YOO ,  Tae Hoon KIM

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  H01L45/143 ,  H01L45/1683

    Abstract: A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a plurality of insulating layers spaced apart from each other in a stacking direction, a slit insulating layer passing through the plurality of insulating layers, a plurality of first variable resistance layers alternately disposed with the plurality of insulating layers in the stacking direction, a plurality of conductive lines interposed between the slit insulating layer and the plurality of first variable resistance layers and alternately disposed with the plurality of insulating layers in the stacking direction, a conductive pillar passing through the plurality of insulating layers and the plurality of first variable resistance layers, and a second variable resistance layer surrounding a sidewall of the conductive pillar.

    ELECTRONIC DEVICE AND METHOD OF OPERATING MEMORY CELL IN THE ELECTRONIC DEVICE
    30.
    发明申请
    ELECTRONIC DEVICE AND METHOD OF OPERATING MEMORY CELL IN THE ELECTRONIC DEVICE 有权

    公开(公告)号：US20210020244A1

    公开(公告)日：2021-01-21

    申请号：US17039480

    申请日：2020-09-30

    Applicant: SK hynix Inc.

    Inventor： Sang Hyun BAN ,  Beom Seok LEE ,  Woo Tae LEE ,  Tae Hoon KIM ,  Hwan Jun ZANG ,  Hye Jung CHOI

    IPC: G11C13/00

    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a word line, a bit line, and a memory cell coupled to and disposed between the word line and the bit line, the memory cell including a variable resistance layer that remains in an amorphous state regardless of a value of data stored in the memory cell. In a reset operation, the memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is greater than 0.7 time of a threshold voltage of the memory cell and is smaller than 0.95 time of the threshold voltage.

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