公开(公告)号：US09853163B2

公开(公告)日：2017-12-26

申请号：US15280879

申请日：2016-09-29

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01J21/105 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78696

Abstract: A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

公开(公告)号：US20170352741A1

公开(公告)日：2017-12-07

申请号：US15664225

申请日：2017-07-31

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Pietro Montanini

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/265 ,  H01L27/092 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66636 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.

公开(公告)号：US20170162554A1

公开(公告)日：2017-06-08

申请号：US14956834

申请日：2015-12-02

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L25/18 ,  H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15156 ,  H01L2924/15313 ,  H01L2924/157

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US20160218070A1

公开(公告)日：2016-07-28

申请号：US15090996

申请日：2016-04-05

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Byoung Youp Kim ,  Walter Kleemeier

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/562 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76897 ,  H01L22/12 ,  H01L22/14 ,  H01L22/32 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the edges of a die to prevent and detect damages to the die. The multilayer structure includes a support layer, a first plurality of dielectric pillars overlying the support layer, a metal layer that fills spaces between the first plurality of dielectric pillars, an insulation layer overlying the first plurality of dielectric pillars and the metal layer, a second plurality of dielectric pillars overlying the insulation layer, and a second metal layer that fills spaces between the second plurality of dielectric pillars.

Abstract translation: 各种实施例便于集成电路的管芯保护。 在一个实施例中，多层结构形成在多个层次上并沿着模具的边缘，以防止和检测对模具的损坏。 所述多层结构包括支撑层，覆盖所述支撑层的第一多个介电柱，填充所述第一多个介电柱之间的空间的金属层，覆盖所述第一多个介电柱和所述金属层的绝缘层，第二 覆盖绝缘层的多个介电柱，以及填充第二多个介电柱之间的空间的第二金属层。

公开(公告)号：US09385177B2

公开(公告)日：2016-07-05

申请号：US14068198

申请日：2013-10-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Edem Wornyo

IPC: H01L49/02 ,  H01L23/525 ,  H01L27/01 ,  H01L21/3105 ,  H01L23/522 ,  H01L21/321

CPC classification number: H01L27/016 ,  H01L21/31053 ,  H01L21/3212 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5252 ,  H01L23/5256 ,  H01L28/20 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method of fabricating such a structure cleverly takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.

Abstract translation: 半导体处理步骤的顺序允许在公共结构内形成垂直和水平的纳米级蛇形电阻器和平行板电容器。 制造这种结构的方法巧妙地利用CMP工艺不均匀性，其中绝缘材料的CMP抛光速率根据某些基础形貌而变化。 通过在绝缘材料层之下建立这样的形貌，可以通过利用差分抛光速率在不同的区域产生绝缘体的不同膜厚度，从而避免使用光刻掩模。 在一个实施例中，使用仅需要两个掩模层的工艺，可以在公共介电块内形成多个电阻器和电容器作为紧凑的集成结构。 这样形成为一组集成电路元件的电阻器和电容器分别适合用作微电子熔丝和反熔丝，以保护下面的微电子电路。

公开(公告)号：US20160099339A1

公开(公告)日：2016-04-07

申请号：US14969911

申请日：2015-12-15

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Pietro Montanini

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/8238

CPC classification number: H01L29/66636 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.

Abstract translation: 集成电路管芯包括硅衬底。 在硅衬底上形成PMOS和NMOS晶体管。 通过向NMOS晶体管的沟道区域引入拉伸应力并进入PMOS晶体管的沟道区域中的压应力来增加PMOS和NMOS晶体管的载流子迁移率。 通过在NMOS晶体管的沟道区域的下方包含SiGe区域来引入拉伸应力。 通过在PMOS晶体管的源极和漏极区域中包括SiGe的区域来引入压缩应力。

公开(公告)号：US09214622B2

公开(公告)日：2015-12-15

申请号：US13645658

申请日：2012-10-05

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L41/09 ,  H01L41/332

CPC classification number: H01L41/332 ,  H01L41/0973

Abstract: A support structure includes an internal cavity. An elastic membrane extends to divide the internal cavity into a first chamber and a second chamber. The elastic membrane includes a nanometric-sized pin hole extending there through to interconnect the first chamber to the second chamber. The elastic membrane is formed of a first electrode film and a second electrode film separated by a piezo insulating film. Electrical connection leads are provided to support application of a bias current to the first and second electrode films of the elastic membrane. In response to an applied bias current, the elastic membrane deforms by bending in a direction towards one of the first and second chambers so as to produce an increase in a diameter of the pin hole.

Abstract translation: 支撑结构包括内腔。 弹性膜延伸以将内腔分成第一腔室和第二腔室。 弹性膜包括在其上延伸的纳米尺寸的针孔，以将第一腔室与第二腔室相互连接。 弹性膜由第一电极膜和由压电绝缘膜隔开的第二电极膜形成。 提供电连接引线以支持向弹性膜的第一和第二电极膜施加偏置电流。 响应于施加的偏置电流，弹性膜通过沿朝向第一和第二腔室之一的方向弯曲而变形，从而产生销孔直径的增加。

公开(公告)号：US20150279784A1

公开(公告)日：2015-10-01

申请号：US14231448

申请日：2014-03-31

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise ,  Terry Spooner ,  Nicole A. Saulnier

IPC: H01L23/532 ,  G03F1/36 ,  H01L21/768

CPC classification number: G03F1/36 ,  G03F1/00 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wavy line interconnect structure that accommodates small metal lines and large vias is disclosed. A lithography mask design used to pattern metal line trenches uses optical proximity correction (OPC) techniques to approximate wavy lines using rectangular opaque features. The large vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. Instead, a sacrificial layer allows etching of an underlying thick dielectric block, while protecting narrow features of the trenches that correspond to the metal line interconnects. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By lifting the shrink constraint for vias, thereby allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

Abstract translation: 公开了一种容纳小金属线和大通孔的波浪线互连结构。 用于图形金属线沟槽的光刻掩模设计使用光学邻近校正（OPC）技术来使用矩形不透明特征来近似波浪线。 可以使用自对准双镶嵌工艺形成大通孔，而不需要单独的通孔光刻掩模。 相反，牺牲层允许蚀刻下面的厚介质块，同时保护对应于金属线互连的沟槽的窄特征。 所得到的通孔具有相对容易填充的纵横比，而较大的通孔覆盖区提供低通孔电阻。 通过提升通孔的收缩约束，从而允许通孔覆盖区超过金属线宽度的最小尺寸，为另外的工艺世代清除了一条路径，以继续将金属线收缩到低于10nm的尺寸。

公开(公告)号：US09136473B2

公开(公告)日：2015-09-15

申请号：US13852050

申请日：2013-03-28

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/06 ,  H01L45/00 ,  B82Y10/00 ,  G11C13/00 ,  H01L27/24 ,  G11C13/02

CPC classification number: H01L45/16 ,  B82Y10/00 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/025 ,  G11C2213/76 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

Abstract: A semiconductor device may include a substrate, and an array of PCM memory cells above the substrate. Each PCM memory cell may include first and second vertically aligned electrodes, a first dielectric layer between the first and second electrodes, a carbon nanotube extending vertically through the first dielectric layer from the second electrode and toward the first electrode, and a PCM body between the first electrode and the at least one carbon nanotube.

Abstract translation: 半导体器件可以包括衬底，以及衬底上方的PCM存储器单元的阵列。 每个PCM存储单元可以包括第一和第二垂直排列的电极，第一和第二电极之间的第一介电层，从第二电极垂直延伸穿过第一介电层并朝向第一电极的碳纳米管， 第一电极和至少一个碳纳米管。

公开(公告)号：US09018092B2

公开(公告)日：2015-04-28

申请号：US13629402

申请日：2012-09-27

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295

Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.

Abstract translation: 多个金属轨道形成在集成电路管芯内，堆叠在管芯内的三个金属层。 在中间金属层的金属轨道周围形成保护电介质层。 保护性介电层用作硬掩模，以在中间金属层之上和之下的金属层中限定金属轨道之间的接触通孔。