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    ROW DECODER CIRCUIT FOR A PHASE CHANGE NON-VOLATILE MEMORY DEVICE
    25.
    发明申请
    ROW DECODER CIRCUIT FOR A PHASE CHANGE NON-VOLATILE MEMORY DEVICE 有权
    相位变化非易失性存储器件的ROW解码器电路

    公开(公告)号：US20130301348A1

    公开(公告)日：2013-11-14

    申请号：US13888593

    申请日：2013-05-07

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Maurizio Francesco Perroni ,  Guido Desandre ,  Salvatore Polizzi ,  Giuseppe Castagna

    IPC: G11C13/00

    CPC classification number: G11C13/0028 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/79

    Abstract: A row decoder circuit for a phase change non-volatile memory device may include memory cells arranged in a wordlines. The device may be configured to receive a first supply voltage and a second supply voltage higher than the first supply voltage. The row decoder may include a global predecoding stage configured to receive address signals and generate high-voltage decoded address signals in a range of the second supply voltage and a biasing signal with a value based upon an operation. The row decoder may include a row decoder stage coupled to the global predecoding stage. The row decoder stage may include a selection driving unit configured to generate block-address signals based upon the high-voltage decoded address signals and a row-driving unit configured to generate a row-driving signal for biasing the wordlines based upon the block-address signals and the biasing signal.

    Abstract translation: 用于相变非易失性存储器件的行解码器电路可以包括以字线布置的存储器单元。 该装置可以被配置为接收高于第一电源电压的第一电源电压和第二电源电压。 行解码器可以包括全局预解码级，其被配置为接收地址信号并且在第二电源电压的范围内产生高电压解码的地址信号，并且基于操作具有基于值的偏置信号。 行解码器可以包括耦合到全局预编码阶段的行解码器级。 行解码器级可以包括：选择驱动单元，被配置为基于高电压解码的地址信号产生块地址信号;以及行驱动单元，被配置为基于块地址生成用于偏置字线的行驱动信号 信号和偏置信号。

    Bit-line voltage generation circuit for a non-volatile memory device and corresponding method
    26.
    发明授权
    Bit-line voltage generation circuit for a non-volatile memory device and corresponding method 有权

    公开(公告)号：US11322201B2

    公开(公告)日：2022-05-03

    申请号：US17159381

    申请日：2021-01-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Maurizio Francesco Perroni ,  Fabio Enrico Carlo Disegni ,  Michele La Placa ,  Cesare Torti

    IPC: G11C13/00

    Abstract: An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.

    NON VOLATILE MEMORY DEVICE WITH AN ASYMMETRIC ROW DECODER AND METHOD FOR SELECTING WORD LINES
    27.
    发明申请
    NON VOLATILE MEMORY DEVICE WITH AN ASYMMETRIC ROW DECODER AND METHOD FOR SELECTING WORD LINES 有权

    公开(公告)号：US20210166745A1

    公开(公告)日：2021-06-03

    申请号：US17088060

    申请日：2020-11-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fabio Enrico Carlo Disegni ,  Maurizio Francesco Perroni ,  Cesare Torti ,  Guiseppe Scardino

    IPC: G11C8/10 ,  G11C8/08

    Abstract: A non-volatile memory device including an array of memory cells coupled to word lines and a row decoder, which includes a first and a second pull-down stage, which are arranged on opposite sides of the array, and include, respectively, for each word line, a corresponding first pull-down switching circuit and a corresponding second pull-down switching circuit, which are coupled to a first point and a second point, respectively, of the first word line. The row decoder moreover comprises a pull-up stage, which includes, for each word line, a corresponding pull-up switching circuit, which can be electronically controlled in order to: couple the first point to a supply node in the step of deselection of the word line; and decouple the first point from the supply node in the step of selection of the word line.

    Level Shifter Circuit Having Two-Domain Level Shifting Capability
    29.
    发明申请
    Level Shifter Circuit Having Two-Domain Level Shifting Capability 审中-公开

    公开(公告)号：US20190287633A1

    公开(公告)日：2019-09-19

    申请号：US16294386

    申请日：2019-03-06

    Applicant: STMicroelectronics S.r.l.

    Inventor： Antonino Conte ,  Leopoldo Maria Marino ,  Maurizio Francesco Perroni ,  Salvatore Polizzi

    IPC: G11C16/34 ,  G11C5/14 ,  G11C8/08 ,  G11C16/20 ,  H03K19/00

    Abstract: A level shifter circuit configured to shift an input signal switching within a first voltage range to generate a first output signal correspondingly switching within a second voltage range higher than the first voltage range. The level shifter circuit including a latching core having latching input and output terminals and a supply line configured to be supplied by a supply voltage, and a reference line configured to be coupled to a reference voltage. Capacitive coupling elements are coupled to the latching input and output terminals of the latching core. A driving stage is configured to bias the capacitive coupling elements with biasing signals generated based on the input signal. A decoupling stage is configured to be driven by the driving stage through the capacitive coupling elements to decouple the supply line from the supply voltage and the reference line from the reference voltage during switching of the input signal.

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