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公开(公告)号：US10262708B2
公开(公告)日：2019-04-16
申请号：US15825504
申请日：2017-11-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byunghoon Jeong , Jeongdon Ihm
IPC: G11C8/12 , H01L21/822 , G11C16/16 , H01L27/11556 , G11C16/04 , G11C7/22 , G11C29/02 , G11C16/34 , H01L27/06 , H01L21/3213
Abstract: A memory system may include a nonvolatile memory device and a controller. The nonvolatile memory device may include a data area and a device information area, the device information area being inaccessible accessed by a host. The controller may be configured to perform the training operation with respect to a data signal transmitted to or received from the nonvolatile memory device based on training information stored in the device information area. The controller may be configured to select one of a first training operation and a second training operation based on an identification code of the training information, and to perform the selected one of the first training operation based on a rooted training code generated by the controller and the second training operation based on a dynamic training code of the training information, the second training operation including performing a fewer number of searches than the first training operation.
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22.发明授权公开(公告)号：US12217793B2
公开(公告)日：2025-02-04
申请号：US17852035
申请日：2022-06-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eunjin Song , Kyoungtae Kang , Sanglok Kim , Chiweon Yoon , Byunghoon Jeong
IPC: G11C11/4096 , G11C11/4074 , G11C11/4093 , G11C11/4094
Abstract: A data transfer circuit in a nonvolatile memory device includes first repeaters, second repeaters and signal lines. The signal lines connect the first repeaters and the second repeaters, and include a first group of signal lines and a second group of signal lines alternatingly arranged. The first repeaters include a first group of repeaters activated in a first operation mode and a second group of repeaters activated in a second operation mode. The second repeaters include a third group of repeaters activated in the first operation mode and are connected to the first group of repeaters through the first group of signal lines floated in the second operation mode, and a fourth group of repeaters activated in the second operation mode and are connected to the second group of repeaters through the second group of signal lines floated in the first operation mode.
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公开(公告)号：US11783874B2
公开(公告)日：2023-10-10
申请号：US17470579
申请日：2021-09-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Taehyeon Park , Byunghoon Jeong , Chiweon Yoon
CPC classification number: G11C7/1012 , G11C7/109 , G11C7/1057 , G11C7/1063 , G11C7/1084 , G11C7/20 , G11C8/06
Abstract: A memory chip, a memory controller, and an operating method of the memory chip are provided. The memory chip includes a plurality of pins; and an interface circuit configured to receive a swap command set from a memory controller through the plurality of pins, obtain a swap command and a swap address from the swap command set, generate a swap enable signal based on the swap command and the swap address, and swap and output a data signal according to the swap enable signal.
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公开(公告)号：US11562780B2
公开(公告)日：2023-01-24
申请号：US17411421
申请日：2021-08-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byunghoon Jeong , Kyungtae Kang , Jangwoo Lee , Jeongdon Ihm
IPC: G11C7/22 , G11C7/10 , H03K19/173 , G11C8/18 , G11C29/42
Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
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公开(公告)号：US11522550B2
公开(公告)日：2022-12-06
申请号：US17077891
申请日：2020-10-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Anil Kavala , Seonkyoo Lee , Taesung Lee , Jeongdon Ihm , Byunghoon Jeong
Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.
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Patent Agency Ranking
公开(公告)号：US11336266B2
公开(公告)日：2022-05-17
申请号：US17222033
申请日：2021-04-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongho Shin , Kyungtae Kang , Junha Lee , Tongsung Kim , Jangwoo Lee , Jeongdon Ihm , Byunghoon Jeong
Abstract: A method of operating a system including a parameter monitoring circuit and a host, includes generating a first parameter applying a first code to a current parameter, wherein a first offset is applied to the first code; generating a first comparison result by comparing the first parameter with a reference parameter value; generating a second parameter applying a second code to the current parameter, wherein a second offset is applied to the second code; generating a second comparison result by comparing the second parameter with the reference parameter value; detecting an error in the current parameter, based on the first comparison result and the second comparison result; and providing a signal based on the error to the host.
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公开(公告)号：US11315614B2
公开(公告)日：2022-04-26
申请号：US17150307
申请日：2021-01-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Daehoon Na , Jeongdon Ihm , Jangwoo Lee , Byunghoon Jeong
Abstract: A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.
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公开(公告)号：US20180204773A1
公开(公告)日：2018-07-19
申请号：US15825504
申请日：2017-11-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byunghoon Jeong , Jeongdon IHM
IPC: H01L21/822 , G11C16/16 , H01L27/11556 , G11C16/04
CPC classification number: G11C8/12 , G11C7/222 , G11C16/0483 , G11C16/16 , G11C16/3445 , G11C29/023 , G11C29/028 , G11C2207/2254 , H01L21/32137 , H01L21/8221 , H01L27/0688 , H01L27/11556
Abstract: A memory system may include a nonvolatile memory device and a controller. The nonvolatile memory device may include a data area and a device information area, the device information area being inaccessible accessed by a host. The controller may be configured to perform the training operation with respect to a data signal transmitted to or received from the nonvolatile memory device based on training information stored in the device information area. The controller may be configured to select one of a first training operation and a second training operation based on an identification code of the training information, and to perform the selected one of the first training operation based on a rooted training code generated by the controller and the second training operation based on a dynamic training code of the training information, the second training operation including performing a fewer number of searches than the first training operation.
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公开(公告)号：US09767873B2
公开(公告)日：2017-09-19
申请号：US15198564
申请日：2016-06-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seonkyoo Lee , Taesung Lee , Jeongdon Ihm , Byunghoon Jeong
CPC classification number: G11C7/22 , G06F11/10 , G11C7/106 , G11C7/1066 , G11C7/1087 , G11C7/1093 , G11C16/32
Abstract: A semiconductor device of the inventive concept includes a timing circuit configured to receive a first timing signal of a first pulse width from an external device and output a second timing signal having a pulse width which is gradually being reduced from a second pulse width longer than the pulse width of the first timing signal, and a data input/output circuit receiving the second timing signal and outputting data to the external device in synchronization with the second timing signal.
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公开(公告)号：US09330781B2
公开(公告)日：2016-05-03
申请号：US14546039
申请日：2014-11-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sungjun Kim , Sangtae Kim , Byunghoon Jeong
CPC classification number: G11C17/18 , G11C13/0007 , G11C13/004 , G11C17/16 , G11C17/165 , G11C29/78 , G11C2013/0042 , G11C2213/71 , G11C2213/72
Abstract: A nonvolatile memory device is provided. The nonvolatile memory device includes a memory cell array, an anti-fuse cell array, a sense amplifier, a page buffer, and a control logic. The memory cell array includes memory cells connected to word lines and bit lines. The anti-fuse cell array stores setting information for controlling the memory cell array. The anti-fuse cell array includes anti-fuse cells connected to the bit lines. The sense amplifier is connected to the bit lines to sense the memory cells or the anti-fuse cells. The page buffer stores data that is read out from the memory cells or the anti-fuse cells. The control logic controls the sense amplifiers and the page buffer to read out data from the memory cell array or the anti-fuse cell array.
Abstract translation: 提供非易失性存储器件。 非易失性存储器件包括存储单元阵列，反熔丝单元阵列，读出放大器，页面缓冲器和控制逻辑。 存储单元阵列包括连接到字线和位线的存储单元。 反熔丝单元阵列存储用于控制存储单元阵列的设置信息。 反熔丝单元阵列包括连接到位线的反熔丝单元。 读出放大器连接到位线以感测存储单元或反熔丝单元。 页面缓冲器存储从存储单元或反熔丝单元读出的数据。 控制逻辑控制读出放大器和页缓冲器从存储单元阵列或反熔丝单元阵列中读出数据。
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