公开(公告)号：US20170338825A1

公开(公告)日：2017-11-23

申请号：US15599191

申请日：2017-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoon Lee ,  Donghun Lee ,  Jaewon Lee

IPC: H03L7/081 ,  H03L7/091 ,  H03K19/20

CPC classification number: H03L7/0818 ,  H03K5/131 ,  H03K19/20 ,  H03K2005/00234 ,  H03L7/0816 ,  H03L7/085 ,  H03L7/091 ,  H03L7/10

Abstract: A delay locked loop includes a delay line, a delay circuit, a phase detector, a delay code generator, and a delay controller. The delay line may delay an input clock signal in units of unit delay in response to a delay control code to generate an output clock signal. The delay circuit may delay the output clock signal to generate a delay clock signal. The phase detector may compare the input clock signal and the delay clock signal to generate a phase detection signal. The delay code generator may compare the input clock signal and the delay clock signal to detect a phase difference therebetween, and generate a delay code using the phase difference. The delay controller may generate the delay control code using the delay code and the phase detection signal.

公开(公告)号：US12125553B2

公开(公告)日：2024-10-22

申请号：US17968052

申请日：2022-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghun Lee ,  Kiho Kim ,  Kihan Kim

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C7/1084 ,  G11C2207/2254

Abstract: Disclosed are a memory device that performs offset calibration and a method of operating the memory device. The memory device includes an input/output pad configured to receive data from a device external, an on-die termination (ODT) circuit connected to the input/output pad, a plurality of receivers connected to the ODT circuit and configured to receive the data from the input/output pad, an offset calibration circuit configured to perform an offset calibration operation on data output from the plurality of receivers and output an offset correction, a first switch configured to provide a first voltage to the plurality of receivers, and a second switch configured to provide a second voltage to the plurality of receivers. During the offset calibration operation, the plurality of receivers receive a third voltage in response to the ODT circuit being enabled and the first voltage through the first switch.

公开(公告)号：US11062744B2

公开(公告)日：2021-07-13

申请号：US16262250

申请日：2019-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Lee ,  Daesik Moon ,  Young-Soo Sohn ,  Young-Hoon Son ,  Ki-Seok Oh ,  Changkyo Lee ,  Hyun-Yoon Cho ,  Kyung-Soo Ha ,  Seokhun Hyun

IPC: G11C7/10 ,  G06F3/06

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

公开(公告)号：US10741564B2

公开(公告)日：2020-08-11

申请号：US15255652

申请日：2016-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghun Lee ,  TaeYong Kwon ,  Dongwon Kim

IPC: H01L27/11 ,  H01L27/11582 ,  H01L27/092 ,  H01L29/417

Abstract: An SRAM device includes first, second and third transistors, which are used as a pass gate transistor, a pull-down transistor, and a pull-up transistor, respectively. A channel region of each transistor may include a plurality of semiconductor sheets that are vertically stacked on a substrate. The semiconductor sheets used as the channel regions of the first and second transistors may have a width greater than the semiconductor sheets used as channel regions of the third transistor.

公开(公告)号：US10559673B2

公开(公告)日：2020-02-11

申请号：US16284843

申请日：2019-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungil Park ,  Changhee Kim ,  Yunil Lee ,  Mirco Cantoro ,  Junggun You ,  Donghun Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/28 ,  H01L29/40 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417

Abstract: A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater width than the active pillar. A first insulating layer is disposed on a sidewall of the active pillar and a second insulating layer is disposed on at least a bottom surface of the first source/drain region. A gate electrode is disposed on the first insulating layer and the second insulating layer. A second source/drain region is disposed in the substrate at a bottom end of the active pillar. Methods of fabrication are also described.

公开(公告)号：US20180248018A1

公开(公告)日：2018-08-30

申请号：US15664226

申请日：2017-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil Park ,  Changhee Kim ,  Yunil Lee ,  Mirco Cantoro ,  Junggun You ,  Donghun Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/28 ,  H01L29/40

CPC classification number: H01L29/66666 ,  H01L21/28114 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/401 ,  H01L29/4238 ,  H01L29/66553 ,  H01L29/7827

Abstract: A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater width than the active pillar. A first insulating layer is disposed on a sidewall of the active pillar and a second insulating layer is disposed on at least a bottom surface of the first source/drain region. A gate electrode is disposed on the first insulating layer and the second insulating layer. A second source/drain region is disposed in the substrate at a bottom end of the active pillar. Methods of fabrication are also described.