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公开(公告)号：US20150029790A1
公开(公告)日：2015-01-29
申请号：US14485049
申请日：2014-09-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SANG-WAN NAM , WON-TEACK JUNG , JUNGHOON PARK
CPC classification number: G11C16/14 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/3418 , G11C16/344 , G11C16/3445 , H01L27/115
Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.
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22.发明公开公开(公告)号：US20240161816A1
公开(公告)日：2024-05-16
申请号：US18377751
申请日：2023-10-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： SEONGJIN KIM , SANG-WAN NAM , Sungho MOON
IPC: G11C11/4099 , G11C5/14 , G11C11/4074 , G11C11/4096
CPC classification number: G11C11/4099 , G11C5/147 , G11C11/4074 , G11C11/4096
Abstract: A memory device may include a reference voltage generator that generates a reference voltage, a voltage regulator that includes a plurality of driving blocks generating an internal voltage based on the reference voltage, and a power line that receives the internal voltage. At least one of the plurality of driving blocks may include a first unit driver that generates a first output current flowing through the power line based on the reference voltage and a change in the internal voltage, and a second unit driver that generates a second output current larger than the first output current flowing through the power line, based on the reference voltage and the change in the internal voltage. The first unit driver may generate the first output current faster than the second output current of the second unit driver.
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23.发明公开公开(公告)号：US20230154553A1
公开(公告)日：2023-05-18
申请号：US17955858
申请日：2022-09-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： YOHAN LEE , SANG-WAN NAM , SANG-WON PARK , JIHO CHO , EUNHYANG PARK
CPC classification number: G11C16/3459 , G11C16/102 , G11C16/24 , G11C16/3404
Abstract: Disclosed is an operation method of a memory device that includes a plurality of memory cells stacked in a direction perpendicular to a substrate. The method includes performing first to (n−1)-th program loops on selected memory cells connected to a selected word line from among the plurality of memory cells, based on a first program parameter, and after the (n−1)-th program loop is performed, performing n-th to k-th program loops on the selected memory cells, based on a second program parameter different from the first program parameter. Herein, n is an integer greater than 1 and k is an integer greater than or equal to n. The first and second program parameters include information about at least two of a program voltage increment, a 2-step verify range, and a bit line forcing voltage used in the first to k-th program loops.
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公开(公告)号：US20230133286A1
公开(公告)日：2023-05-04
申请号：US17871358
申请日：2022-07-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： YOU-SE KIM , SANG-WAN NAM , KEE HO JUNG
Abstract: A nonvolatile memory device includes: a memory cell array including three or more planes; a first clock generator generating a first clock signal having a first period; a second clock generator generating a second clock signal having a second period that varies with the temperature; a plurality of clock switching controllers outputting one of the first and second clock signals as a reference clock signal; a control logic including a plurality of bitline shutoff generators, which output a plurality of bitline shutoff signals based on the reference clock signal; and a plurality of page buffers connecting bitlines of the planes and data latch nodes in accordance with the bitline shutoff signals.
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公开(公告)号：US20220130467A1
公开(公告)日：2022-04-28
申请号：US17377141
申请日：2021-07-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： JAE-DUK YU , SANG-WAN NAM , JONGHOON PARK , HO-JUN LEE
Abstract: An operation method of a nonvolatile memory device includes receiving a read command and an address, increasing a voltage applied to an unselected word line from an off voltage to a read pass voltage during a setup phase in response to the read command, increasing a voltage applied to an unselected string selection line from the off voltage to a pre-pulse voltage during a first setup phase of the setup phase, increasing a voltage applied to an unselected ground selection line from the off voltage to the pre-pulse voltage during the first setup phase, applying a read voltage to a selected word line to read data corresponding to the address, during a sensing phase following the setup phase, and outputting the read data through data lines after the sensing phase. During the setup phase, a slope of the voltage applied to the unselected word line is varied.
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Patent Agency Ranking
公开(公告)号：US20200168547A1
公开(公告)日：2020-05-28
申请号：US16592886
申请日：2019-10-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： BONGSOON LIM , SANG-WAN NAM , SANG-WON PARK , SANG-WON SHIM , HONGSOO JEON , YONGHYUK CHOI
IPC: H01L23/535 , H01L27/11582 , H01L27/11573
Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.
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公开(公告)号：US20190088341A1
公开(公告)日：2019-03-21
申请号：US15959323
申请日：2018-04-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： WON-TAECK JUNG , SO-YEONG GWAK , SANG-WAN NAM
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/34 , G11C16/3459
Abstract: An operation method of a nonvolatile memory device includes applying a program voltage to a selected word line and programming a selected memory cell connected to the selected word line; reading an adjacent memory cell connected to an adjacent word line of the selected word line; and verifying the selected memory cell by adjusting charge sharing between the selected memory cell and a sensing node, which is connected to the selected memory cell through a bit line.
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28.发明申请公开(公告)号：US20180204620A1
公开(公告)日：2018-07-19
申请号：US15816903
申请日：2017-11-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： WANDONG KIM , SANG-SOO PARK , SE HWAN PARK , SANG-WAN NAM
IPC: G11C16/08
CPC classification number: G11C16/08 , G11C8/08 , G11C16/0483 , G11C16/20 , G11C16/26
Abstract: A nonvolatile memory device performs a method which includes: causing a ready/busy signal pin of the nonvolatile memory device to indicate that the nonvolatile memory device is in a precharge busy state wherein the nonvolatile memory device is not available to perform memory access operations for its nonvolatile memory cells; applying one or more word line precharge voltages to one or more selected word lines among a plurality of word lines of the nonvolatile memory device to precharge the selected word lines; and, after at least a portion of the precharge operation, causing the ready/busy signal pin to transition from indicating the precharge busy state, to indicating that the nonvolatile memory device is in a ready state wherein the nonvolatile memory device is available to perform memory access operations for its nonvolatile memory cells.
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公开(公告)号：US20160343443A1
公开(公告)日：2016-11-24
申请号：US15229158
申请日：2016-08-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： YOON-HEE CHOI , SANG-WAN NAM , KANG-BIN LEE
CPC classification number: G11C16/10 , G11C7/04 , G11C11/5628 , G11C16/0483 , G11C16/16 , G11C16/30 , G11C16/3459
Abstract: In a method of programming a three-dimensional nonvolatile memory device, a program loop is executed at least one time, wherein the program loop includes a programming step for programming selected memory cells among the memory cells and a verifying step for verifying whether the selected memory cells are program-passed or not. In the programming the selected memory cells, a level of a voltage being applied to a common source line connected to the strings in common may be changed. Thus, in a program operation, power consumption which is needed to charge-discharge the common source line can be decreased while increasing boosting efficiency.
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公开(公告)号：US20150340097A1
公开(公告)日：2015-11-26
申请号：US14716550
申请日：2015-05-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： TAE-HYUN KIM , YOUNG-SUN MIN , SUNG-WHAN SEO , WON-TAE KIM , SANG-WAN NAM
CPC classification number: G11C16/26 , G11C5/147 , G11C7/04 , G11C16/30 , G11C16/349 , G11C29/021 , G11C29/028 , H02M3/158
Abstract: A voltage generator includes a first trim unit and a second trim unit. The first trim unit generates a first voltage variable depending on temperature variation and a second voltage invariable irrespective of the temperature variation based on a power supply voltage, and performs a first trim operation by changing a level of the second voltage. The level of the second voltage at a first temperature becomes substantially the same as a level of the first voltage at the first temperature based on the first trim operation. The second trim unit generates an output voltage based on the power supply voltage, the first and second voltages, a reference voltage and a feedback voltage, and performs a second trim operation by adjusting variation of the output voltage depending on the temperature variation based on a result of the first trim operation.
Abstract translation: 电压发生器包括第一调整单元和第二调整单元。 第一微调单元根据温度变化产生第一电压变量，而不管基于电源电压的温度变化而产生第二电压，并且通过改变第二电压的电平来执行第一微调操作。 基于第一调整操作，第一温度下的第二电压的电平变得与第一温度下的第一电压的电平基本相同。 第二微调单元基于电源电压，第一和第二电压，参考电压和反馈电压产生输出电压，并且通过基于温度变化调整输出电压的变化来执行第二微调操作 第一次修剪操作的结果。
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