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21.发明授权公开(公告)号：US11086224B2
公开(公告)日：2021-08-10
申请号：US16676588
申请日：2019-11-07
发明人： Keunhee Bai , Jinhong Park , Jinseok Heo , Seungmin Lee , Suntaek Lim
IPC分类号： G03F7/20 , H01L21/268
摘要： Disclosed are a system for fabricating a semiconductor device and a method of fabricating a semiconductor device. The system may include a chamber, an extreme ultraviolet (EUV) source in the chamber and configured to generate an EUV beam, an optical system on the EUV source and configured to provide the EUV beam to a substrate, a substrate stage in the chamber and configured to receive the substrate, a reticle stage in the chamber and configured to hold a reticle that is configured to project the EUV beam onto the substrate, and a particle collector between the reticle and the optical system and configured to allow for a selective transmission of the EUV beam and to remove a particle.
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公开(公告)号：US10651668B2
公开(公告)日：2020-05-12
申请号：US15056296
申请日：2016-02-29
发明人： Youngjun Choi , Seungmin Lee , Heon Chol Kim , Ikhyun Cho
IPC分类号： H02J7/00 , G06F1/16 , G06F1/26 , G06F1/3231 , G06F1/3287 , A45F5/02
摘要： A power control method and an electronic device and/or connecting unit to implement the power control method is provided. The electronic device includes a first interface unit configured to be connected to an external device that can receive and provide power to the electronic device, a second interface unit configured to be connected to an external charger that can provide power for the external device and the electronic device, and a main controller configured to detect whether or not the external charger is connected, and receive and direct power from the external device or the external charger according to whether or not the external charger is connected.
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公开(公告)号：US12087879B2
公开(公告)日：2024-09-10
申请号：US18303423
申请日：2023-04-19
发明人： Euijoon Yoon , Jehong Oh , Jungel Ryu , Seungmin Lee , Jongmyeong Kim
IPC分类号： H01L33/00 , H01L25/075 , H01L33/16 , H01L33/24 , H01L33/32
CPC分类号： H01L33/24 , H01L25/0753 , H01L33/0095 , H01L33/16 , H01L33/32
摘要： Disclosed are a display device and a manufacturing method thereof. The display device includes a plurality of pixels, a light emitting device provided in each of the plurality of pixels, the light emitting device having a first surface and a second surface, which are opposite to each other, a first electrode electrically connected to the first surface of the light emitting device, a second electrode electrically connected to the second surface of the light emitting device, and a metal oxide pattern interposed between the second surface of the light emitting device and the second electrode. The metal oxide pattern is provided to cover a portion of the second surface and to expose a remaining portion of the second surface. The second electrode is electrically connected to the exposed remaining portion of the second surface, and the metal oxide pattern includes single-crystalline or polycrystalline alumina.
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24.发明公开公开(公告)号：US20240266344A1
公开(公告)日：2024-08-08
申请号：US18422924
申请日：2024-01-25
发明人： Seungmin Lee , Changbeom Kim , Jungho Do , Wookyu Kim
IPC分类号： H01L27/02 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L27/0207 , H01L27/092 , H01L29/0665 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696
摘要： An integrated circuit includes a power rail extending in a first direction and configured to receive a supply voltage, a gate line below the power rail and extending in a second direction that intersects the first direction, a source/drain region adjacent to the gate line in the first direction and configured to receive the supply voltage from the power rail, a frontside wiring layer above the power rail, connected to the power rail, and configured to transmit the supply voltage to the power rail, and a backside wiring layer below the power rail, connected to the power rail, and configured to transmit the supply voltage to the power rail.
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公开(公告)号：US20240196617A1
公开(公告)日：2024-06-13
申请号：US18511396
申请日：2023-11-16
发明人： Seungmin Lee , Jihwan Yu , Byungman Ahn , Bonghyun Choi
IPC分类号： H10B43/27 , G11C16/04 , H01L25/065 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/35 , H10B80/00
CPC分类号： H10B43/27 , G11C16/0483 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/35 , H10B80/00 , H01L2225/06506
摘要： A semiconductor device includes a substrate comprising a chip region and a scribe lane region including a first key pattern region, a capping insulating layer disposed on the scribe lane region, a barrier metal layer covering the capping insulating layer and an inner wall of a via hole penetrating the capping insulating layer, a substrate layer disposed on the barrier metal layer and filling the via hole, an insulating plate and an upper base layer disposed on the substrate layer, a pattern insulating layer disposed on the capping insulating layer in the first key pattern region, a stacked structure disposed on the upper base layer and the pattern insulating layer, and first pattern structures overlapping the pattern insulating layer in a vertical direction and penetrating the stacked structure and the pattern insulating layer, wherein the pattern insulating layer extends through the barrier metal layer in the first key pattern region.
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公开(公告)号：US20240147692A1
公开(公告)日：2024-05-02
申请号：US18496211
申请日：2023-10-27
发明人： Seungmin Lee
IPC分类号： H10B12/00
摘要： A semiconductor memory device of the present invention is capable of high performance and high integration, and has an effect of configuring a semiconductor die including a vertical volatile memory structure and a vertical nonvolatile memory structure on one peripheral circuit structure. A semiconductor memory device provided includes a semiconductor substrate, a back gate structure having a cylindrical shape and extending in a vertical direction on the semiconductor substrate and including a back gate electrode layer and a back gate insulating layer surrounding the back gate electrode layer, a plurality of semiconductor patterns, each having a ring-shaped horizontal section surrounding the back gate structure, and spaced apart from each other in the vertical direction, and first to third conductive lines surrounding one of the plurality of semiconductor patterns and spaced apart from each other in the vertical direction.
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公开(公告)号：US20230363157A1
公开(公告)日：2023-11-09
申请号：US18352182
申请日：2023-07-13
发明人： Junhyoung Kim , Jisung Cheon , Yoonhwan Son , Seungmin Lee
摘要： A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.
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公开(公告)号：USD800587S1
公开(公告)日：2017-10-24
申请号：US29555244
申请日：2016-02-19
设计人： Chul-Ho Cho , Myeong Su Cheon , Sangkyu Kim , Seungmin Lee
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