公开(公告)号：US20230197811A1

公开(公告)日：2023-06-22

申请号：US18171502

申请日：2023-02-20

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Minhyun LEE ,  Minsu SEOL ,  Ho Won JANG ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/423 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/1606 ,  H01L29/66439

Abstract: Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.

公开(公告)号：US20230155017A1

公开(公告)日：2023-05-18

申请号：US18157478

申请日：2023-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/778 ,  H01L27/092 ,  H01L29/24 ,  H01L29/78 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7788 ,  H01L27/092 ,  H01L29/24 ,  H01L29/7831 ,  H01L29/78642 ,  H01L29/41741

Abstract: A vertical type transistor includes: a substrate; a first source/drain electrode layer provided on the substrate; a second source/drain electrode layer provided above the first source/drain electrode layer; a first gate electrode layer provided between the first and second source/drain electrode layers; a first gate insulating film passing through the first gate electrode layer; a hole passing through the second source/drain electrode layer, the first gate insulating film, and the first source/drain electrode layer; and a first channel layer provided on a lateral side of the hole, wherein the first channel layer may include a 2D semiconductor.

公开(公告)号：US20210234015A1

公开(公告)日：2021-07-29

申请号：US17060696

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Minhyun LEE ,  Minsu SEOL ,  Ho Won JANG ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/06 ,  H01L29/04 ,  H01L29/66

Abstract: Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.

公开(公告)号：US20210163296A1

公开(公告)日：2021-06-03

申请号：US17060893

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Van Luan NGUYEN ,  Keunwook SHIN ,  Hyeonjin SHIN ,  Changhyun KIM ,  Changseok LEE ,  Yeonchoo CHO

IPC: C01B32/186

Abstract: A method of forming graphene includes: preparing a substrate in a reaction chamber; performing a first growth process of growing a plurality of graphene aggregates apart from each other on the substrate at a first growth rate by using a reaction gas including a carbon source; and performing a second growth process of forming a graphene layer by growing the plurality of graphene aggregates at a second growth rate slower than the first growth rate by using the reaction gas including the carbon source.

公开(公告)号：US20210074815A1

公开(公告)日：2021-03-11

申请号：US17087968

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Hyeonjin SHIN ,  Yeonchoo CHO ,  Seunggeol NAM ,  Seongjun PARK ,  Yunseong LEE

IPC: H01L29/16 ,  H01L21/02 ,  C01B32/186

Abstract: Provided is a semiconductor device including graphene. The semiconductor device includes: a substrate including an insulator and a semiconductor; and a graphene layer configured to directly grow only on a surface of the semiconductor, wherein the semiconductor includes at least one of a group IV material and a group III-V compound.

公开(公告)号：US20200294928A1

公开(公告)日：2020-09-17

申请号：US16884590

申请日：2020-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun BYUN ,  Keunwook SHIN ,  Yonghoon KIM ,  Hyeonjin SHIN ,  Hyunjae SONG ,  Changseok LEE ,  Changhyun KIM ,  Yeonchoo CHO

IPC: H01L23/532

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

公开(公告)号：US20200286732A1

公开(公告)日：2020-09-10

申请号：US16807702

申请日：2020-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Janghee LEE ,  Seunggeol NAM ,  Hyeonjin SHIN ,  Hyunseok LIM ,  Alum JUNG ,  Kyung-Eun BYUN ,  Jeonil LEE ,  Yeonchoo CHO

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/26

Abstract: Provided are a method of pre-treating a substrate and a method of directly forming graphene by using the method of pre-treating the substrate. In the method of pre-treating the substrate in the method of directly forming graphene, according to an embodiment, the substrate is pre-treated by using a pre-treatment gas including at least a carbon source and hydrogen. The method of directly forming graphene includes a process of pre-treating a substrate and a process of directly growing graphene on the substrate that is pre-treated. The process of pre-treating the substrate is performed according to the method of pre-treating the substrate.

公开(公告)号：US20160291472A1

公开(公告)日：2016-10-06

申请号：US14843003

申请日：2015-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjin SHIN ,  Sangwon KIM ,  Minsu SEOL ,  Seongjun PARK ,  Yeonchoo CHO

IPC: G03F7/11 ,  G03F7/36 ,  G03F7/16

Abstract: A hardmask composition may include graphene nanoparticles having a size in a range of about 5 nm to about 100 nm and a solvent.

Abstract translation: 硬掩模组合物可以包括尺寸在约5nm至约100nm范围内的石墨烯纳米颗粒和溶剂。

公开(公告)号：US20160282721A1

公开(公告)日：2016-09-29

申请号：US14825792

申请日：2015-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Sangwon KIM ,  Hyeonjin SHIN ,  Seongjun PARK ,  Yeonchoo CHO

IPC: G03F7/11

CPC classification number: G03F7/094

Abstract: A hardmask composition includes a plurality of graphene nanosheets doped with boron (B) and/or nitrogen (N) and a solvent. A size of the graphene nanosheet may be in a range of about 5 nm to about 1000 nm. The hardmask composition may include an aromatic ring-containing material.

Abstract translation: 硬掩模组合物包括掺杂有硼（B）和/或氮（N）和溶剂的多个石墨烯纳米片。 石墨烯纳米片的尺寸可以在约5nm至约1000nm的范围内。 硬掩模组合物可以包括含芳环的材料。

公开(公告)号：US20160240482A1

公开(公告)日：2016-08-18

申请号：US14814938

申请日：2015-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae SONG ,  Seunggeol NAM ,  Yeonchoo CHO ,  Seongjun PARK ,  Hyeonjin SHIN ,  Jaeho LEE

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53209 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/5226

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

Abstract translation: 示例实施例涉及具有扩散阻挡层的层结构及其制造方法。 层结构包括第一和第二材料层以及它们之间的扩散阻挡层。 扩散阻挡层包括纳米晶石墨烯（nc-G）层。 在层结构中，扩散阻挡层还可以与nc-G层一起包括非石墨烯金属化合物层或石墨烯层。 第一和第二材料层之一是绝缘层，金属层或半导体层，其余层可以是金属层。