公开(公告)号：US20240203945A1

公开(公告)日：2024-06-20

申请号：US18419399

申请日：2024-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Jinwoo Park ,  Jaekyung Yoo ,  Teakhoon Lee

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L23/295 ,  H01L23/3135 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/17 ,  H01L24/33 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/17181 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92143 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: A semiconductor package includes a package substrate on which a base chip is disposed. A first semiconductor chip is disposed on the base chip. A second semiconductor chip is disposed on the first semiconductor chip. An inner mold layer surrounds an upper surface of the base chip and respective side surfaces of the first semiconductor chip and the second semiconductor chip. A first outer mold layer is interposed between the package substrate and the base chip while covering at least a portion of a side surface of the base chip. A second outer mold layer is disposed on the first outer mold layer while covering at least a portion of a side surface of the inner mold layer. The second outer mold layer is spaced apart from the package substrate. The first outer mold layer and the second outer mold layer have different viscosities.

公开(公告)号：US11594499B2

公开(公告)日：2023-02-28

申请号：US17203007

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon Ko ,  Un-Byoung Kang ,  Jaekyung Yoo ,  Teak Hoon Lee

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/13

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

公开(公告)号：US11538792B2

公开(公告)日：2022-12-27

申请号：US17140241

申请日：2021-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Jayeon Lee ,  Jae-eun Lee ,  Yeongkwon Ko ,  Jin-woo Park ,  Teak Hoon Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/13 ,  H01L23/498 ,  H01L25/00

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

公开(公告)号：US20220375808A1

公开(公告)日：2022-11-24

申请号：US17879272

申请日：2022-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon Ko ,  Seunghun Shin ,  Junyeong Heo

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes: a first semiconductor chip including a first surface and a second surface opposite to each other and including first through electrodes; at least a second semiconductor chip stacked on the first surface of the first semiconductor chip and comprising second through electrodes electrically connected to the first through electrodes; and a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip and including a first external side wall connected to and on the same plane as a side wall of the first semiconductor chip, wherein the first external side wall of the molding layer extends to be inclined with respect to a first direction orthogonal to the first surface of the first semiconductor chip, and both the external first side wall of the molding layer and the side wall of the first semiconductor chip have a first slope that is the same for both the first external side wall of the molding layer and the side wall of the first semiconductor chip.

公开(公告)号：US20210050264A1

公开(公告)日：2021-02-18

申请号：US16871189

申请日：2020-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghoon WON ,  Jaeeun Lee ,  Yeongkwon Ko ,  Junyeong Heo

IPC: H01L21/78 ,  H01L21/268

Abstract: There is provided a method of dicing a semiconductor wafer, which includes providing a semiconductor substrate having a plurality of integrated circuit regions on an active surface of the semiconductor substrate, a dicing regions provided between adjacent integrated circuit regions of the plurality of integrated circuit regions, and a metal shield layer provided on the active surface across at least a portion of the adjacent integrated circuit regions and the dicing region, forming a modified layer by irradiating laser to an inside of the semiconductor substrate along the dicing region, propagating a crack from the modified layer in a direction perpendicular to a major-axial direction of the metal shield layer by polishing an inactive surface opposing the active surface of the semiconductor substrate and forming semiconductor chips by separating the adjacent integrated circuit regions, respectively, based on the crack propagating from the modified layer.

公开(公告)号：US20250167061A1

公开(公告)日：2025-05-22

申请号：US19029411

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Park ,  Jongho Lee ,  Yeongkwon Ko ,  Teakhoon Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.

公开(公告)号：US20240387420A1

公开(公告)日：2024-11-21

申请号：US18438335

申请日：2024-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soyeon Kwon ,  Jihun Jung ,  Yeongkwon Ko

IPC: H01L23/00 ,  H01L25/065

Abstract: The present disclosure relates to a semiconductor package including: a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip; and at least one bump structure disposed between the first semiconductor chip and the second semiconductor chip, wherein the bump structure includes a first bump pad and a second bump pad with different planar areas.

公开(公告)号：US20240321744A1

公开(公告)日：2024-09-26

申请号：US18612137

申请日：2024-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Jiyoung Park ,  Hosin Song ,  Sera Lee

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/48 ,  H01L23/532 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5283 ,  H01L23/481 ,  H01L23/532 ,  H01L25/0657 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2924/1436

Abstract: The present disclosure relates to semiconductor packages. An example semiconductor package includes a substrate including an active surface and an inactive surface, a plurality of wiring structures arranged on the active surface of the substrate, an inter-wiring insulating layer arranged on the active surface of the substrate and configured to cover the plurality of wiring structures, a modified layer including both side surfaces thereof covered by the inter-wiring insulating layer and including a carbonized material, and a passivation layer arranged on the inter-wiring insulating layer and the modified layer.

公开(公告)号：US20240321666A1

公开(公告)日：2024-09-26

申请号：US18675881

申请日：2024-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Jongho Lee ,  Yeongkwon Ko

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L23/3157 ,  H01L21/568 ,  H01L23/293 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1012 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/8185

Abstract: A method of manufacture for a semiconductor package includes; forming a molding member on side surfaces of the semiconductor chips, using an adhesive to attach a carrier substrate to upper surfaces of the molding member and the semiconductor chips, using a first blade having a first blade-width to cut away selected portions of the carrier substrate and portions of the adhesive underlying the selected portions of the carrier substrate, and using the first blade to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are dispose above portions of the molding member between adjacent ones of semiconductor chips, using a second blade having a second blade-width narrower than the first blade-width to cut through a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separate a package structure including a semiconductor chip supported by a cut portion of the carrier substrate and bonding the package structure to an upper surface of a package substrate.

公开(公告)号：US12062639B2

公开(公告)日：2024-08-13

申请号：US17529798

申请日：2021-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Jongho Lee ,  Yeongkwon Ko

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/4803 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/5385 ,  H01L23/562 ,  H01L24/16 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/73204

Abstract: A semiconductor package includes a lower substrate including a central region and an edge region, an upper substrate on the central region of the lower substrate, a first semiconductor chip on the upper substrate, a second semiconductor chip on the upper substrate and horizontally spaced apart from the first semiconductor chip, a reinforcing structure on the edge region of the lower substrate, and a molding layer that covers an inner sidewall of the reinforcing structure, a top surface of the lower substrate, a sidewall of the first semiconductor chip, a sidewall of the second semiconductor chip, and the upper substrate. The molding layer is interposed between the lower substrate and the upper substrate, between the upper substrate and the first semiconductor chip, and between the upper substrate and the second semiconductor chip. The first semiconductor chip is of a different type from the second semiconductor chip.