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    SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS
    21.
    发明申请
    SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS 有权

    公开(公告)号：US20220399343A1

    公开(公告)日：2022-12-15

    申请号：US17568440

    申请日：2022-01-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Wooyoung CHOI ,  Juseong OH ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L49/02 ,  G11C5/10 ,  H01L23/528 ,  H01L23/522

    Abstract: A semiconductor device includes a substrate including a cell area having a first active region and a peripheral circuit area having a second active region, a direct contact contacting the first active region in the cell area, a bit line structure disposed on the direct contact, a capacitor structure electrically connected to the first active region, a gate structure disposed on the second active region in the peripheral circuit area, lower wiring layers disposed adjacent to the gate structure and electrically connected to the second active region, upper wiring layers disposed on the lower wiring layers, a wiring insulating layer disposed between the lower wiring layers and the upper wiring layers, and upper contact plugs connected to at least one of the lower wiring layers and the upper wiring layers and extending through the wiring insulating layer.

    SEMICONDUCTOR MEMORY DEVICE
    22.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210408008A1

    公开(公告)日：2021-12-30

    申请号：US17471824

    申请日：2021-09-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L27/24

    Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

    SEMICONDUCTOR DEVICE INCLUDING STORAGE NODE ELECTRODE INCLUDING STEP AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
    23.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING STORAGE NODE ELECTRODE INCLUDING STEP AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210202490A1

    公开(公告)日：2021-07-01

    申请号：US16943019

    申请日：2020-07-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehwan CHO ,  Junghwan OH ,  Sangho LEE ,  Junwon LEE ,  Jinwoo BAE ,  Sunghee HAN ,  Yoosang HWANG

    IPC: H01L27/108

    Abstract: A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

    SEMICONDUCTOR MEMORY DEVICES
    24.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20210057416A1

    公开(公告)日：2021-02-25

    申请号：US17090419

    申请日：2020-11-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

    SEMICONDUCTOR MEMORY DEVICE
    25.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200043941A1

    公开(公告)日：2020-02-06

    申请号：US16508839

    申请日：2019-07-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung KIM ,  Kiseok LEE ,  Keunnam KIM ,  Yoosang HWANG

    IPC: H01L27/11578 ,  H01L27/1157 ,  H01L27/11573

    Abstract: A semiconductor device may include a stack structure that includes a plurality of layers vertically stacked on a substrate, and a plurality of gate electrodes that vertically extend to penetrate the stack structure. Each of the plurality of layers may include a plurality of semiconductor patterns that extend in parallel along a first direction, a bit line that is electrically connected to the semiconductor patterns and extends in a second direction intersecting the first direction, a first air gap on the bit line, and a data storage element that is electrically connected to a corresponding one of the semiconductor patterns. The first air gap is interposed between the bit line of a first layer of the plurality of layers and the bit line of a second layer of the plurality of layers.

    METHODS FOR FABRICATING SEMICONDUCTOR DEVICES
    28.
    发明申请
    METHODS FOR FABRICATING SEMICONDUCTOR DEVICES 有权
    制造半导体器件的方法

    公开(公告)号：US20150340284A1

    公开(公告)日：2015-11-26

    申请号：US14569980

    申请日：2014-12-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunjung KIM ,  Yong Kwan KIM ,  Jemin PARK ,  Semyeong JANG ,  Sangyeon HAN ,  Yoosang HWANG

    IPC: H01L21/768 ,  H01L29/66

    CPC classification number: H01L27/1288 ,  H01L21/7688 ,  H01L27/10814 ,  H01L27/10891

    Abstract: The present inventive concepts provide methods for fabricating semiconductor devices. The method may comprise providing a substrate, stacking a conductive layer and a lower mask layer on the substrate, forming a plurality of hardmask layers each having an island shape on the lower mask layer, forming a plurality of upper mask patterns having island shapes arranged to expose portions of the lower mask layer, etching the exposed portions of the lower mask layer to expose portions of the conductive layer, and etching the exposed portions of the conductive layer to form a plurality of contact holes each exposing a portion of the substrate.

    Abstract translation: 本发明构思提供了制造半导体器件的方法。 该方法可以包括提供衬底，在衬底上堆叠导电层和下掩模层，在下掩模层上形成各自具有岛状的多个硬掩模层，形成具有岛形的多个上掩模图案，其布置成 暴露下掩模层的部分，蚀刻下掩模层的暴露部分以暴露导电层的部分，并且蚀刻导电层的暴露部分以形成多个接触孔，每个接触孔暴露衬底的一部分。

    SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS
    30.
    发明公开
    SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS 审中-公开

    公开(公告)号：US20240008260A1

    公开(公告)日：2024-01-04

    申请号：US18368939

    申请日：2023-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Wooyoung CHOI ,  Juseong OH ,  Yoosang HWANG

    IPC: H10B12/00 ,  H01L23/522 ,  H01L23/528 ,  G11C5/10

    CPC classification number: H10B12/37 ,  H01L28/60 ,  H01L23/5226 ,  H01L23/528 ,  G11C5/10

    Abstract: A semiconductor device includes a substrate including a cell area having a first active region and a peripheral circuit area having a second active region, a direct contact contacting the first active region in the cell area, a bit line structure disposed on the direct contact, a capacitor structure electrically connected to the first active region, a gate structure disposed on the second active region in the peripheral circuit area, lower wiring layers disposed adjacent to the gate structure and electrically connected to the second active region, upper wiring layers disposed on the lower wiring layers, a wiring insulating layer disposed between the lower wiring layers and the upper wiring layers, and upper contact plugs connected to at least one of the lower wiring layers and the upper wiring layers and extending through the wiring insulating layer.

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