公开(公告)号：US11367714B2

公开(公告)日：2022-06-21

申请号：US16845567

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangwoo Lee ,  Jongbo Shim ,  Ji Hwang Kim ,  Yungcheol Kong ,  Youngbae Kim ,  Taehwan Kim ,  Hyunglak Ma

IPC: H01L25/10 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373

Abstract: A semiconductor package device may include a first package substrate, a first semiconductor chip on the first package substrate, an interposer on the first semiconductor chip, a warpage prevention member on the interposer, a molding member on the interposer and the first package substrate, and a second package substrate on the molding member. At least a portion of a top surface of the molding member may be spaced apart from a bottom surface of the second package substrate.

公开(公告)号：US11152416B2

公开(公告)日：2021-10-19

申请号：US16507623

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Chajea Jo ,  Hyoeun Kim ,  Jongbo Shim ,  Sang-Uk Han

IPC: H01L31/00 ,  H01L27/146 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.

公开(公告)号：US09646895B2

公开(公告)日：2017-05-09

申请号：US14714667

申请日：2015-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungduk Baek ,  Ji Hwang Kim ,  Taeje Cho

IPC: H01L21/66 ,  G01R31/26 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L22/14 ,  G01R31/2601 ,  H01L22/32 ,  H01L23/5256 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor package includes providing a semiconductor chip including a circuit pattern, a connection pad, a first test pad and a second test pad, each of the connection pad, the first test pad and the second test pad respectively electrically connected to the circuit pattern, evaluating electrical characteristics of the semiconductor chip by applying a first test voltage to the first test pad and a second test voltage to the second test pad, the second test voltage being higher than the first test voltage, and electrically disconnecting the second test pad from the circuit pattern.

公开(公告)号：US09425111B2

公开(公告)日：2016-08-23

申请号：US14751626

申请日：2015-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Woo Park ,  Ji Hwang Kim ,  Jongbo Shim

IPC: H01L23/48 ,  H01L21/66 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L22/32 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/49816 ,  H01L25/065 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a package substrate; a semiconductor chip mounted on a top surface of the package substrate; a chip pad disposed on a bottom surface of the semiconductor chip to face the top surface of the package substrate, the chip pad including a connection pad and a measurement pad; and a chip bump including a first bump provided between the package substrate and the connection pad and a second bump provided between the package substrate and the measurement pad. An interconnection disposed within the package substrate is not connected to the second bump to be electrically isolated from the second bump.

Abstract translation: 半导体封装包括封装衬底; 安装在所述封装衬底的顶表面上的半导体芯片; 芯片焊盘，其设置在所述半导体芯片的底面上以面向所述封装基板的上表面，所述芯片焊盘包括连接焊盘和测量焊盘; 以及包括设置在封装基板和连接焊盘之间的第一凸起的芯片凸块和设置在封装基板和测量垫之间的第二凸块。 设置在封装基板内的互连件不与第二凸块连接以与第二凸块电隔离。

公开(公告)号：US08802495B2

公开(公告)日：2014-08-12

申请号：US13955259

申请日：2013-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang Kim ,  Tae Hong Min ,  Chajea Jo ,  Taeje Cho ,  Young Kun Jee ,  Yun Seok Choi

IPC: H01L21/50 ,  H01L21/56

CPC classification number: H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor package includes preparing a parent substrate including package board parts laterally spaced apart from each other, mounting a first chip including a through-via electrode on each of the package board parts, forming a first mold layer on the parent substrate having the first chips, planarizing the first mold layer to expose back sides of the first chips, etching the exposed back sides of the first chips to expose back sides of the through-via electrodes, forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes, and selectively removing the passivation layer to expose the back sides of the through-via electrodes.

Abstract translation: 制造半导体封装的方法包括：准备包括彼此横向隔开的封装板部分的母基板，在每个封装板部件上安装包括通孔电极的第一芯片，在母基板上形成第一模层 具有第一芯片，平坦化第一模具层以暴露第一芯片的背面，蚀刻第一芯片的暴露的背面以暴露通孔电极的背面，在平坦化的第一模具层上形成钝化层， 第一芯片的蚀刻背面和通孔电极的背面，并且选择性地去除钝化层以暴露通孔电极的背面。