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    MOS transistor with elevated source/drain structure
    23.
    发明授权
    MOS transistor with elevated source/drain structure 有权
    具有升高的源极/漏极结构的MOS晶体管

    公开(公告)号：US07368792B2

    公开(公告)日：2008-05-06

    申请号：US11388868

    申请日：2006-03-24

    申请人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

    发明人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7834 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

    摘要： In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

    摘要翻译： 在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是 在形成外延层之后形成，从而防止源极/漏极结区域的劣化。 此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。 这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

    Method of fabricating CMOS transistor and CMOS transistor fabricated thereby
    24.
    发明授权
    Method of fabricating CMOS transistor and CMOS transistor fabricated thereby 有权
    制造CMOS晶体管和CMOS晶体管的方法

    公开(公告)号：US07354835B2

    公开(公告)日：2008-04-08

    申请号：US11157521

    申请日：2005-06-21

    申请人： Dong-suk Shin ,  Hwa-sung Rhee ,  Ueno Tetsuji ,  Ho Lee ,  Seung-hwan Lee

    发明人： Dong-suk Shin ,  Hwa-sung Rhee ,  Ueno Tetsuji ,  Ho Lee ,  Seung-hwan Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66636 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

    摘要： In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes amorphizing the active region of only the second conductivity type MOS transistor, and performing selective etching to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth that is greater than the first depth in the active region of the second conductivity type MOS transistor. Selective epitaxial growth is performed in the first and second recessed regions to form an elevated epitaxial layer that fills the first recessed region and extends to a level that is above the upper surface of the semiconductor substrate and to form a recessed epitaxial layer that fills the second recessed region.

    摘要翻译： 在制造CMOS晶体管的方法和根据该方法制造的CMOS晶体管的情况下，第一和第二导电型MOS晶体管的特性都同时改善。 同时，通过减少所需掩模的数量来简化制造过程。 该方法包括仅使第二导电型MOS晶体管的有源区非晶化，并进行选择性蚀刻，以在第一导电类型MOS晶体管的有源区中形成第一深度的第一凹陷区域和第二深度的第二凹陷区域 大于第二导电类型MOS晶体管的有源区中的第一深度。 在第一和第二凹陷区域中执行选择性外延生长，以形成一个升高的外延层，其填充第一凹陷区域并延伸到半导体衬底的上表面之上的水平面并形成填充第二凹陷区域的凹陷外延层 凹陷区域。

    Method of fabricating CMOS transistor and CMOS transistor fabricated thereby
    25.
    发明申请
    Method of fabricating CMOS transistor and CMOS transistor fabricated thereby 有权
    制造CMOS晶体管和CMOS晶体管的方法

    公开(公告)号：US20050280098A1

    公开(公告)日：2005-12-22

    申请号：US11157521

    申请日：2005-06-21

    申请人： Dong-suk Shin ,  Hwa-sung Rhee ,  Ueno Tetsuji ,  Ho Lee ,  Seung-hwan Lee

    发明人： Dong-suk Shin ,  Hwa-sung Rhee ,  Ueno Tetsuji ,  Ho Lee ,  Seung-hwan Lee

    IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/76

    CPC分类号： H01L29/66636 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

    摘要： In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes amorphizing the active region of only the second conductivity type MOS transistor, and performing selective etching to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth that is greater than the first depth in the active region of the second conductivity type MOS transistor. Selective epitaxial growth is performed in the first and second recessed regions to form an elevated epitaxial layer that fills the first recessed region and extends to a level that is above the upper surface of the semiconductor substrate and to form a recessed epitaxial layer that fills the second recessed region.

    摘要翻译： 在制造CMOS晶体管的方法和根据该方法制造的CMOS晶体管的情况下，第一和第二导电型MOS晶体管的特性都同时改善。 同时，通过减少所需掩模的数量来简化制造过程。 该方法包括仅使第二导电型MOS晶体管的有源区非晶化，并进行选择性蚀刻，以在第一导电类型MOS晶体管的有源区中形成第一深度的第一凹陷区域和第二深度的第二凹陷区域 大于第二导电类型MOS晶体管的有源区中的第一深度。 在第一和第二凹陷区域中执行选择性外延生长，以形成一个升高的外延层，其填充第一凹陷区域并延伸到半导体衬底的上表面之上的水平面并形成填充第二凹陷区域的凹陷外延层 凹陷区域。

    Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same
    28.
    发明授权
    Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same 有权
    具有具有改善的操作和闪烁噪声特性的模拟晶体管的半导体器件及其制造方法

    公开(公告)号：US07952147B2

    公开(公告)日：2011-05-31

    申请号：US11802281

    申请日：2007-05-22

    申请人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

    发明人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

    IPC分类号： H01L21/70

    CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7848

    摘要： A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.

    摘要翻译： 具有改善的晶体管操作和闪烁噪声特性的半导体器件包括衬底，模拟NMOS晶体管和设置在衬底上的压缩应变通道模拟PMOS晶体管。 该器件还包括分别覆盖NMOS晶体管和PMOS晶体管的第一蚀刻停止衬垫（ESL）和第二ESL。 在500 Hz频率下，NMOS和PMOS晶体管的闪烁噪声功率相对于参考无约束通道模拟NMOS和PMOS晶体管的闪烁噪声功率的相对测量值小于1。

    Bipolar device and method of manufacturing the same including pre-treatment using germane gas
    30.
    发明授权
    Bipolar device and method of manufacturing the same including pre-treatment using germane gas 失效
    双极装置及其制造方法，包括使用锗烷气体的预处理

    公开(公告)号：US07084041B2

    公开(公告)日：2006-08-01

    申请号：US10795175

    申请日：2004-03-05

    申请人： Hwa-sung Rhee ,  Jae-yoon Yoo ,  Ho Lee ,  Seung-hwan Lee ,  Byou-ree Lim

    发明人： Hwa-sung Rhee ,  Jae-yoon Yoo ,  Ho Lee ,  Seung-hwan Lee ,  Byou-ree Lim

    IPC分类号： H01L21/331

    CPC分类号： H01L29/66287 ,  H01L29/0804 ,  H01L29/7375 ,  H01L29/7378

    摘要： A method of manufacturing a bipolar device including pre-treatment using germane gas and a bipolar device manufactured by the same. The method includes forming a single crystalline silicon layer for a base region on a collector region; and forming a polysilicon layer for an emitter region thereon. Here, before the polysilicon layer is formed, the single crystalline silicon layer is pre-treated using germane gas. Thus, an oxide layer is removed from the single crystalline silicon layer, and a germanium layer is formed on the single crystalline silicon layer, thus preventing Si-rearrangement.

    摘要翻译： 一种制造双极器件的方法，其包括使用锗烷气体的预处理和由其制造的双极器件。 该方法包括在集电区上形成用于基区的单晶硅层; 并在其上形成发射极区的多晶硅层。 这里，在形成多晶硅层之前，使用锗烷气预处理单晶硅层。 因此，从单晶硅层去除氧化物层，并且在单晶硅层上形成锗层，从而防止Si重排。