公开(公告)号：US20100276703A1

公开(公告)日：2010-11-04

申请号：US12837408

申请日：2010-07-15

Applicant: Satoshi Tanimoto

Inventor： Satoshi Tanimoto

IPC: H01L31/0312

CPC classification number: H01L29/7802 ,  H01L21/0485 ,  H01L21/049 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/94

Abstract: A MOS type SiC semiconductor device having high reliability and a longer lifespan against TDDB of a gate oxide film is disclosed. The semiconductor device includes a MOS (metal-oxide-semiconductor) structure having a silicon carbide (SiC) substrate, a polycrystalline Si gate electrode, a gate oxide film interposed between the SiC substrate and the polycrystalline Si gate electrode and formed by thermally oxidizing a surface of the SiC substrate, and an ohmic contact electrically contacted with the SiC substrate. The semiconductor device further includes a polycrystalline Si thermally-oxidized film formed by oxidizing a surface of the polycrystalline Si gate electrode. The gate oxide film has a thickness of 20 nm or less, preferably 15 nm or less.

Abstract translation: 公开了一种对栅极氧化膜的TDDB具有高可靠性和较长使用寿命的MOS型SiC半导体器件。 半导体器件包括具有碳化硅（SiC）衬底的MOS（金属氧化物半导体）结构，多晶Si栅电极，介于SiC衬底和多晶Si栅电极之间的栅极氧化膜，并通过热氧化 SiC衬底的表面和与SiC衬底电接触的欧姆接触。 半导体器件还包括通过氧化多晶Si栅电极的表面而形成的多晶Si热氧化膜。 栅氧化膜的厚度为20nm以下，优选为15nm以下。

公开(公告)号：US07772058B2

公开(公告)日：2010-08-10

申请号：US12022607

申请日：2008-01-30

Applicant: Satoshi Tanimoto

Inventor： Satoshi Tanimoto

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/7802 ,  H01L21/0485 ,  H01L21/049 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/94

Abstract: A MOS type SiC semiconductor device having high reliability and a longer lifespan against TDDB of a gate oxide film is disclosed. The semiconductor device includes a MOS (metal-oxide-semiconductor) structure having a silicon carbide (SiC) substrate, a polycrystalline Si gate electrode, a gate oxide film interposed between the SiC substrate and the polycrystalline Si gate electrode and formed by thermally oxidizing a surface of the SiC substrate, and an ohmic contact electrically contacted with the SiC substrate. The semiconductor device further includes a polycrystalline Si thermally-oxidized film formed by oxidizing a surface of the polycrystalline Si gate electrode. The gate oxide film has a thickness of 20 nm or less, preferably 15 nm or less.

Abstract translation: 公开了一种对栅极氧化膜的TDDB具有高可靠性和较长使用寿命的MOS型SiC半导体器件。 半导体器件包括具有碳化硅（SiC）衬底的MOS（金属氧化物半导体）结构，多晶Si栅电极，介于SiC衬底和多晶Si栅电极之间的栅极氧化膜，并通过热氧化 SiC衬底的表面和与SiC衬底电接触的欧姆接触。 半导体器件还包括通过氧化多晶Si栅电极的表面而形成的多晶Si热氧化膜。 栅氧化膜的厚度为20nm以下，优选为15nm以下。

公开(公告)号：US20080204802A1

公开(公告)日：2008-08-28

申请号：US12037919

申请日：2008-02-26

Applicant: Satoshi Tanimoto

Inventor： Satoshi Tanimoto

IPC: G06K15/00

CPC classification number: H04N1/32133 ,  H04N1/00127 ,  H04N1/00342

Abstract: A communication apparatus includes: a receiving unit which receives reception data transmitted from an external apparatus; an acquiring unit which acquires identification information for identifying the external apparatus which transmits the reception data; and a tag writer which wirelessly write the identification information into a wireless tag.

Abstract translation: 一种通信装置，包括：接收单元，其接收从外部设备发送的接收数据; 获取单元，其获取用于识别发送所述接收数据的外部设备的识别信息; 以及将识别信息无线地写入无线标签的标签写入器。

公开(公告)号：US20070138482A1

公开(公告)日：2007-06-21

申请号：US11634390

申请日：2006-12-06

Applicant: Satoshi Tanimoto

Inventor： Satoshi Tanimoto

IPC: H01L31/0312

CPC classification number: H01L29/1608 ,  H01L21/0465 ,  H01L21/0485 ,  H01L21/0495 ,  H01L29/45 ,  H01L29/6606 ,  H01L29/66068

Abstract: A silicon carbide semiconductor device, includes: 1) a silicon carbide substrate; 2) a silicide electrode configured to be formed by depositing a contact parent material on the silicon carbide substrate in such a manner as to cause a solid phase reaction, the silicide electrode being a lower carbon content silicide electrode including: i) silicon, and ii) carbon smaller than the silicon in mol number; and 3) an upper conductor film deposited to the silicide electrode.

Abstract translation: 一种碳化硅半导体器件，包括：1）碳化硅衬底; 2）一种硅化物电极，其被配置为通过以导致固相反应的方式沉积在碳化硅衬底上的接触母材形成，硅化物电极是低碳含量的硅化物电极，其包括：i）硅和ii ）碳小于硅的摩尔数; 和3）沉积到硅化物电极上的上导体膜。

公开(公告)号：US20050205941A1

公开(公告)日：2005-09-22

申请号：US11069997

申请日：2005-03-03

Applicant: Satoshi Tanimoto

Inventor： Satoshi Tanimoto

IPC: H01L21/28 ,  H01L21/04 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/0485 ,  H01L21/046

Abstract: An aspect of the present invention provides an ohmic electrode that includes an SiC (silicon carbide) substrate, an impurity region selectively formed in a surface of the SiC substrate, an insulating film formed on the surface of the SiC substrate, a contact hole opened through the insulating film, to expose a surface of the impurity region, a conductive thermal reaction layer formed in the contact hole in contact with the impurity region, a conductive plug formed to fill the contact hole, an metal wiring formed on the insulating film and electrically coupled to the plug, and a diffusion preventive layer formed between the metal wiring and the plug to electrically couple the plug with the metal wiring, the diffusion preventive layer configured to prevent the diffusion of metal atoms from the metal wiring.

Abstract translation: 本发明的一个方面提供了一种欧姆电极，其包括SiC（碳化硅）衬底，选择性地形成在SiC衬底的表面中的杂质区域，形成在SiC衬底的表面上的绝缘膜， 所述绝缘膜暴露出所述杂质区的表面，形成在与所述杂质区接触的所述接触孔中的导电性热反应层，形成为填充所述接触孔的导电性插塞，形成在所述绝缘膜上的金属布线， 耦合到所述插头，以及形成在所述金属布线和所述插头之间以将所述插头与所述金属布线电耦合的防扩散层，所述扩散防止层被配置为防止金属原子从所述金属布线扩散。

公开(公告)号：US06833562B2

公开(公告)日：2004-12-21

申请号：US10307363

申请日：2002-12-02

Applicant: Satoshi Tanimoto ,  Hideyo Okushi

Inventor： Satoshi Tanimoto ,  Hideyo Okushi

IPC: H01L310312

CPC classification number: H01L29/66068 ,  H01L29/1608 ,  H01L29/7395 ,  H01L29/7828 ,  H01L29/94

Abstract: In silicon carbide semiconductor device and manufacturing method therefor, a metal electrode which is another than a gate electrode and which is contacted with a singlecrystalline silicon carbide substrate is treated with a predetermined heat process at a temperature which is lower than a thermal oxidization temperature by which a gate insulating film is formed and is sufficient to carry out a contact annealing between the singlecrystalline silicon carbide substrate and a metal after a whole surrounding of the gate insulating film is enclosed with the singlecrystalline silicon carbide substrate, a field insulating film, and the gate electrode. The present invention is applicable to a MOS capacitor, an n channel planar power MOSFET, and an n channel planar power IGBT.

Abstract translation: 在碳化硅半导体器件及其制造方法中，以与栅极电极不同且与单晶碳化硅基板接触的金属电极在预定的热处理下，在低于热氧化温度的温度下进行处理， 形成栅极绝缘膜，并且足以在单晶碳化硅衬底和金属之间进行接触退火，整个栅极绝缘膜周围被单晶碳化硅衬底，场绝缘膜和栅极封闭 电极。 本发明可应用于MOS电容器，n沟道平面功率MOSFET和n沟道平面功率IGBT。

公开(公告)号：US06263277B1

公开(公告)日：2001-07-17

申请号：US09633244

申请日：2000-08-07

Applicant: Satoshi Tanimoto ,  Koichi Endo ,  David Hayes

Inventor： Satoshi Tanimoto ,  Koichi Endo ,  David Hayes

IPC: G06F16500

CPC classification number: G01C21/3446 ,  G01C21/32

Abstract: A method of route searching in a navigation apparatus used to search out a route leading to a destination. Map information is produced by having the nodes on both ends of a link, the length of the link, the speed limit in the link, and the functional class of the link included in the link information. In making the route search, the speed limit in the link is corrected on the basis of the straight line distance to the destination and the functional class of the link, the time for traveling a link is calculated on the basis of the corrected speed limit and the link length, and the route minimizing the time required for reaching a destination is searched out on the basis of the link passing time. In the described case, the functional class is determined using road factors such as the width, speed limit, and type of the road. Correction is made such that the speed limit on higher class links becomes larger and the speed limit on lower class links becomes smaller. Also, the time necessary to pass through an intersection is estimated based on the functional classes of the traveled and intersecting links.

Abstract translation: 用于搜索通向目的地的路线的导航装置中的路线搜索的方法。 通过在链路的两端具有节点，链路的长度，链路中的速度限制以及包括在链路信息中的链路的功能类来产生地图信息。 在进行路线搜索时，基于与目的地的直线距离和链路的功能等级来校正链路中的速度限制，基于修正的速度限制来计算行驶路段的时间， 基于链路通过时间搜索链路长度和最小化到达目的地所需时间的路由。 在描述的情况下，使用道路因素来确定功能等级，例如道路的宽度，速度限制和类型。 进行校正，使得较高级联链路的速度限制变大，下级链路的速度限制变小。 此外，通过交叉路口所需的时间是根据旅行和相交链路的功能类别来估计的。

公开(公告)号：US08975182B2

公开(公告)日：2015-03-10

申请号：US14234476

申请日：2012-07-27

Applicant: Satoshi Tanimoto ,  Yusuke Zushi ,  Yoshinori Murakami ,  Takashi Iseki ,  Masato Takamori ,  Shinji Sato ,  Kohei Matsui

Inventor： Satoshi Tanimoto ,  Yusuke Zushi ,  Yoshinori Murakami ,  Takashi Iseki ,  Masato Takamori ,  Shinji Sato ,  Kohei Matsui

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  B23K35/28 ,  B23K35/00 ,  B23K35/02 ,  C22C18/04 ,  B23K1/00 ,  B23K1/008 ,  B23K1/19 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/1602 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/19 ,  B23K1/206 ,  B23K35/007 ,  B23K35/025 ,  B23K35/282 ,  B23K35/286 ,  B23K2101/34 ,  B23K2101/40 ,  B23K2101/42 ,  C22C18/04 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L29/1608 ,  H01L29/2003 ,  H01L2224/29118 ,  H01L2224/32225 ,  H01L2224/83001 ,  H01L2224/83203 ,  H01L2224/83447 ,  H01L2224/83815 ,  H01L2924/01322 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/01013 ,  H01L2924/0103 ,  H01L2924/00

Abstract: A method for manufacturing a semiconductor device is carried out by readying each of a semiconductor element, a substrate having Cu as a principal element at least on a surface, and a ZnAl solder chip having a smaller shape than that of the semiconductor element; disposing the semiconductor element and the substrate so that respective bonding surfaces face each other, and sandwiching the ZnAl eutectic solder chip between the substrate and the semiconductor element; increasing the temperature of the ZnAl solder chip sandwiched between the substrate and the semiconductor element while applying a load to the ZnAl solder chip such that the ZnAl solder chip melts to form a ZnAl solder layer; and reducing the temperature of the ZnAl solder layer while applying a load to the ZnAl solder layer.

Abstract translation: 半导体器件的制造方法是通过将半导体元件，至少具有表面的Cu作为主要元素的基板和比半导体元件的形状小的ZnAl焊料芯片进行准位来进行的。 将所述半导体元件和所述基板配置为使得各个接合面彼此面对，并将所述ZnAl共晶焊料夹在所述基板和所述半导体元件之间; 在向ZnAl焊料芯片施加负载的同时，增加夹在基板和半导体元件之间的ZnAl焊料芯片的温度，使得ZnAl焊料芯片熔化形成ZnAl焊料层; 并且在向ZnAl焊料层施加负载的同时降低ZnAl焊料层的温度。

公开(公告)号：US08222648B2

公开(公告)日：2012-07-17

申请号：US11991249

申请日：2006-08-22

Applicant: Satoshi Tanimoto ,  Noriaki Kawamoto ,  Takayuki Kitou ,  Mineo Miura

Inventor： Satoshi Tanimoto ,  Noriaki Kawamoto ,  Takayuki Kitou ,  Mineo Miura

IPC: H01L29/24

CPC classification number: H01L29/66068 ,  H01L21/049 ,  H01L21/31666 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7395 ,  H01L29/7802

Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).

Abstract translation: 碳化硅半导体器件（90）包括：1）碳化硅衬底（1）; 2）由多晶硅制成的栅电极（7） 和3）夹在所述碳化硅衬底（1）和所述栅电极（7）之间的ONO绝缘膜（9），从而形成栅极结构，所述ONO绝缘膜（9）包括从所述碳化硅衬底 （1）：a）第一氧化硅膜（O）（10），b）SiN膜（N）（11），和c）SiN热氧化膜（O）（12,12a，12b）。 氮在以下位置中的至少一个中包括：i）在第一氧化物硅膜（O）（10）中和在碳化硅衬底（1）附近，以及ii）在碳化硅衬底 （1）和第一氧化硅膜（O）（10）。

公开(公告)号：US20110017991A1

公开(公告)日：2011-01-27

申请号：US12934199

申请日：2009-02-27

Applicant: Satoshi Tanimoto ,  Norihiko Kiritani ,  Toshiharu Makino ,  Masahiko Ogura ,  Norio Tokuda ,  Hiromitsu Kato ,  Hideyo Okushi ,  Satoshi Yamasaki

Inventor： Satoshi Tanimoto ,  Norihiko Kiritani ,  Toshiharu Makino ,  Masahiko Ogura ,  Norio Tokuda ,  Hiromitsu Kato ,  Hideyo Okushi ,  Satoshi Yamasaki

IPC: H01L29/12 ,  H01L29/06 ,  H01L29/22 ,  H01L29/16 ,  H01L29/24 ,  H01L29/20

CPC classification number: H01L29/861 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/45 ,  H01L29/452 ,  H01L29/456 ,  H01L29/47 ,  H01L29/475 ,  H01L29/872

Abstract: In this junction element 1, when a forward voltage is applied, a depletion layer is formed in a semiconductor layer 2, prohibiting electrons present in an electrode layer 4 to move into the semiconductor layer 2. For this reason, a majority of holes in a semiconductor layer 3 do not disappear by recombination with conduction electrons in the semiconductor layer 2, but reach the electrode layer 4 while diffusing into the semiconductor layer 2. Accordingly, the junction element 1 can serve as a good conductor for holes, while avoiding the influence of a resistance value, and allows a current to flow therethrough at a level equal to or more than that achieved by a semiconductor element formed of a Si or SiC semiconductor. The present invention is applicable to any semiconductor material in which at least one of a donor level and an acceptor level is located at a sufficiently deep position beyond a thermal excitation energy at an operating temperature, such as diamond, zinc oxide (ZnO), aluminum nitride (AlN), or boron nitride (BN). The present invention is also applicable to even a material having a shallow impurity level at room temperature, such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or germanium (Ge), as long as operation is performed at such a low temperature that the thermal excitation energy can be sufficiently small.

Abstract translation: 在该接合元件1中，当施加正向电压时，在半导体层2中形成耗尽层，禁止存在于电极层4中的电子移动到半导体层2中。因此，大部分孔 半导体层3不会通过与半导体层2中的导电电子的复合而消失，而是在扩散到半导体层2中的同时到达电极层4.因此，接合元件1可以用作孔的良导体，同时避免影响 的电阻值，并且允许电流以等于或大于由Si或SiC半导体形成的半导体元件实现的电平流过。 本发明可应用于任何半导体材料，其中施主电平和受主电平中的至少一个位于超过工作温度下的热激发能的足够深的位置，例如金刚石，氧化锌（ZnO），铝 氮化物（AlN）或氮化硼（BN）。 本发明甚至也可应用于诸如硅（Si），碳化硅（SiC），氮化镓（GaN），砷化镓（GaAs）或锗（Ge）等室温下具有浅杂质水平的材料， 只要在如此低的温度下进行操作即可使热激发能足够小。