公开(公告)号：US20090050898A1

公开(公告)日：2009-02-26

申请号：US11991249

申请日：2006-08-22

Applicant: Satoshi Tanimoto ,  Noriaki Kawamoto ,  Takayuki Kitou ,  Mineo Miura

Inventor： Satoshi Tanimoto ,  Noriaki Kawamoto ,  Takayuki Kitou ,  Mineo Miura

IPC: H01L29/24 ,  H01L21/316

CPC classification number: H01L29/66068 ,  H01L21/049 ,  H01L21/31666 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7395 ,  H01L29/7802

Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).

Abstract translation: 碳化硅半导体器件（90）包括：1）碳化硅衬底（1）; 2）由多晶硅制成的栅电极（7） 和3）夹在所述碳化硅衬底（1）和所述栅电极（7）之间的ONO绝缘膜（9），从而形成栅极结构，所述ONO绝缘膜（9）包括从所述碳化硅衬底 （1）：a）第一氧化硅膜（O）（10），b）SiN膜（N）（11），和c）SiN热氧化膜（O）（12,12a，12b）。 氮在以下位置中的至少一个中包括：i）在第一氧化物硅膜（O）（10）中和在碳化硅衬底（1）附近，以及ii）在碳化硅衬底 （1）和第一氧化硅膜（O）（10）。

公开(公告)号：US07329614B2

公开(公告)日：2008-02-12

申请号：US11592165

申请日：2006-11-03

Applicant: Satoshi Tanimoto

Inventor： Satoshi Tanimoto

IPC: H01L21/469

CPC classification number: H01L21/0485 ,  H01L21/046

Abstract: An aspect of the present invention provides an ohmic electrode that includes an SiC (silicon carbide) substrate, an impurity region selectively formed in a surface of the SiC substrate, an insulating film formed on the surface of the SiC substrate, a contact hole opened through the insulating film, to expose a surface of the impurity region, a conductive thermal reaction layer formed in the contact hole in contact with the impurity region, a conductive plug formed to fill the contact hole, an metal wiring formed on the insulating film and electrically coupled to the plug, and a diffusion preventive layer formed between the metal wiring and the plug to electrically couple the plug with the metal wiring, the diffusion preventive layer configured to prevent the diffusion of metal atoms from the metal wiring.

Abstract translation: 本发明的一个方面提供了一种欧姆电极，其包括SiC（碳化硅）衬底，选择性地形成在SiC衬底的表面中的杂质区域，形成在SiC衬底的表面上的绝缘膜， 所述绝缘膜暴露出所述杂质区的表面，形成在与所述杂质区接触的所述接触孔中的导电性热反应层，形成为填充所述接触孔的导电性插塞，形成在所述绝缘膜上的金属布线， 耦合到所述插头，以及形成在所述金属布线和所述插头之间以将所述插头与所述金属布线电耦合的防扩散层，所述扩散防止层被配置为防止金属原子从所述金属布线扩散。

公开(公告)号：US20050093000A1

公开(公告)日：2005-05-05

申请号：US11003599

申请日：2004-12-06

Applicant: Satoshi Tanimoto ,  Hideyo Okushi

Inventor： Satoshi Tanimoto ,  Hideyo Okushi

IPC: H01L21/04 ,  H01L29/12 ,  H01L29/24 ,  H01L29/739 ,  H01L29/78 ,  H01L29/94 ,  H01L29/15 ,  H01L21/00

CPC classification number: H01L29/66068 ,  H01L29/1608 ,  H01L29/7395 ,  H01L29/7828 ,  H01L29/94

Abstract: In silicon carbide semiconductor device and manufacturing method therefor, a metal electrode which is another than a gate electrode and which is contacted with a singlecrystalline silicon carbide substrate is treated with a predetermined heat process at a temperature which is lower than a thermal oxidization temperature by which a gate insulating film is formed and is sufficient to carry out a contact annealing between the singlecrystalline silicon carbide substrate and a metal after a whole surrounding of the gate insulating film is enclosed with the singlecrystalline silicon carbide substrate, a field insulating film, and the gate electrode. The present invention is applicable to a MOS capacitor, an n channel planar power MOSFET, and an n channel planar power IGBT.

Abstract translation: 在碳化硅半导体器件及其制造方法中，以与栅极电极不同且与单晶碳化硅基板接触的金属电极在预定的热处理下，在低于热氧化温度的温度下进行处理， 形成栅极绝缘膜，并且足以在单晶碳化硅衬底和金属之间进行接触退火，整个栅极绝缘膜周围被单晶碳化硅衬底，场绝缘膜和栅极封闭 电极。 本发明可应用于MOS电容器，n沟道平面功率MOSFET和n沟道平面功率IGBT。

公开(公告)号：US06256579B1

公开(公告)日：2001-07-03

申请号：US09352444

申请日：1999-07-13

Applicant: Satoshi Tanimoto

Inventor： Satoshi Tanimoto

IPC: G01C2100

CPC classification number: G01C21/3484

Abstract: The present invention provides a vehicle navigation system that can customize an optimum route to the driver's road preference. The vehicle navigation system includes at least one data table that contains a set of road data. Each set of road data represents characteristics of one road segment, such as a travel time, a length and a type of the road segment. The navigation system also includes at least one coefficient table that contains a number of coefficients. Each coefficient corresponds to one road segment. In a route search operation, an optimum route is calculated so as to optimize road data that have been modified by weighting the road data by the coefficients. The coefficients are changed based on the user's personal preference on the corresponding road segments. More specifically, a coefficient is penalized when the corresponding road segment that was part of the optimum route was not traveled. On the other hand, a coefficient is credited when the corresponding road segment that was not part of the optimum route was actually traveled.

Abstract translation: 本发明提供一种车辆导航系统，其可以根据驾驶员的道路偏好来定制最佳路线。 车辆导航系统包括至少一个包含一组道路数据的数据表。 每组道路数据表示一条路段的特征，例如行驶时间，路段的长度和类型。 导航系统还包括至少一个包含多个系数的系数表。 每个系数对应于一个路段。 在路线搜索操作中，计算最佳路线，以便通过系数对道路数据进行加权来优化已经修改的道路数据。 系数根据用户对相应路段的个人喜好而改变。 更具体地，当作为最佳路线的一部分的对应的路段未行进时，系数被惩罚。 另一方面，当不是最佳路线的一部分的对应路段实际行驶时，系数被记入。

公开(公告)号：US5674563A

公开(公告)日：1997-10-07

申请号：US305536

申请日：1994-09-14

Applicant: Yasuo Tarui ,  Yoshihiro Soutome ,  Shinichi Morita ,  Satoshi Tanimoto

Inventor： Yasuo Tarui ,  Yoshihiro Soutome ,  Shinichi Morita ,  Satoshi Tanimoto

IPC: C01G25/00 ,  C23C16/06 ,  C23C16/40 ,  C23C16/44 ,  C30B29/32 ,  H01G4/10 ,  H01G4/12 ,  H01G4/33 ,  C23C16/00

CPC classification number: C23C16/45561 ,  C23C16/409

Abstract: A ferroelectric thin film is produced on a substrate placed in an oxygen gas atmosphere within a reaction chamber. Evaporated source materials (organic metal compounds) are separately introduced in a predetermined sequence into the reaction chamber to produce a PZT or PLZT layer structure having an estimated stoichiometric composition. This cycle of introduction of the source materials is repeated continuously to produce a PZT or PLZT ferroelectric thin film having a predetermined number of PZT or PLZT layer structures piled on the substrate.

Abstract translation: 在放置在反应室内的氧气气氛中的基板上产生铁电薄膜。 将蒸发源材料（有机金属化合物）以预定顺序分别引入反应室中以产生具有估计化学计量组成的PZT或PLZT层结构。 连续重复引入源材料的这个循环，以产生具有预定数量的PZT或PLZT层结构的PZT或PLZT铁电薄膜，该PZT或PLZT层结构堆叠在基板上。

公开(公告)号：US08975182B2

公开(公告)日：2015-03-10

申请号：US14234476

申请日：2012-07-27

Applicant: Satoshi Tanimoto ,  Yusuke Zushi ,  Yoshinori Murakami ,  Takashi Iseki ,  Masato Takamori ,  Shinji Sato ,  Kohei Matsui

Inventor： Satoshi Tanimoto ,  Yusuke Zushi ,  Yoshinori Murakami ,  Takashi Iseki ,  Masato Takamori ,  Shinji Sato ,  Kohei Matsui

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  B23K35/28 ,  B23K35/00 ,  B23K35/02 ,  C22C18/04 ,  B23K1/00 ,  B23K1/008 ,  B23K1/19 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/1602 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/19 ,  B23K1/206 ,  B23K35/007 ,  B23K35/025 ,  B23K35/282 ,  B23K35/286 ,  B23K2101/34 ,  B23K2101/40 ,  B23K2101/42 ,  C22C18/04 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L29/1608 ,  H01L29/2003 ,  H01L2224/29118 ,  H01L2224/32225 ,  H01L2224/83001 ,  H01L2224/83203 ,  H01L2224/83447 ,  H01L2224/83815 ,  H01L2924/01322 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/01013 ,  H01L2924/0103 ,  H01L2924/00

Abstract: A method for manufacturing a semiconductor device is carried out by readying each of a semiconductor element, a substrate having Cu as a principal element at least on a surface, and a ZnAl solder chip having a smaller shape than that of the semiconductor element; disposing the semiconductor element and the substrate so that respective bonding surfaces face each other, and sandwiching the ZnAl eutectic solder chip between the substrate and the semiconductor element; increasing the temperature of the ZnAl solder chip sandwiched between the substrate and the semiconductor element while applying a load to the ZnAl solder chip such that the ZnAl solder chip melts to form a ZnAl solder layer; and reducing the temperature of the ZnAl solder layer while applying a load to the ZnAl solder layer.

Abstract translation: 半导体器件的制造方法是通过将半导体元件，至少具有表面的Cu作为主要元素的基板和比半导体元件的形状小的ZnAl焊料芯片进行准位来进行的。 将所述半导体元件和所述基板配置为使得各个接合面彼此面对，并将所述ZnAl共晶焊料夹在所述基板和所述半导体元件之间; 在向ZnAl焊料芯片施加负载的同时，增加夹在基板和半导体元件之间的ZnAl焊料芯片的温度，使得ZnAl焊料芯片熔化形成ZnAl焊料层; 并且在向ZnAl焊料层施加负载的同时降低ZnAl焊料层的温度。

公开(公告)号：US08222648B2

公开(公告)日：2012-07-17

申请号：US11991249

申请日：2006-08-22

Applicant: Satoshi Tanimoto ,  Noriaki Kawamoto ,  Takayuki Kitou ,  Mineo Miura

Inventor： Satoshi Tanimoto ,  Noriaki Kawamoto ,  Takayuki Kitou ,  Mineo Miura

IPC: H01L29/24

CPC classification number: H01L29/66068 ,  H01L21/049 ,  H01L21/31666 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7395 ,  H01L29/7802

Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).

Abstract translation: 碳化硅半导体器件（90）包括：1）碳化硅衬底（1）; 2）由多晶硅制成的栅电极（7） 和3）夹在所述碳化硅衬底（1）和所述栅电极（7）之间的ONO绝缘膜（9），从而形成栅极结构，所述ONO绝缘膜（9）包括从所述碳化硅衬底 （1）：a）第一氧化硅膜（O）（10），b）SiN膜（N）（11），和c）SiN热氧化膜（O）（12,12a，12b）。 氮在以下位置中的至少一个中包括：i）在第一氧化物硅膜（O）（10）中和在碳化硅衬底（1）附近，以及ii）在碳化硅衬底 （1）和第一氧化硅膜（O）（10）。

公开(公告)号：US20110017991A1

公开(公告)日：2011-01-27

申请号：US12934199

申请日：2009-02-27

Applicant: Satoshi Tanimoto ,  Norihiko Kiritani ,  Toshiharu Makino ,  Masahiko Ogura ,  Norio Tokuda ,  Hiromitsu Kato ,  Hideyo Okushi ,  Satoshi Yamasaki

Inventor： Satoshi Tanimoto ,  Norihiko Kiritani ,  Toshiharu Makino ,  Masahiko Ogura ,  Norio Tokuda ,  Hiromitsu Kato ,  Hideyo Okushi ,  Satoshi Yamasaki

IPC: H01L29/12 ,  H01L29/06 ,  H01L29/22 ,  H01L29/16 ,  H01L29/24 ,  H01L29/20

CPC classification number: H01L29/861 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/45 ,  H01L29/452 ,  H01L29/456 ,  H01L29/47 ,  H01L29/475 ,  H01L29/872

Abstract: In this junction element 1, when a forward voltage is applied, a depletion layer is formed in a semiconductor layer 2, prohibiting electrons present in an electrode layer 4 to move into the semiconductor layer 2. For this reason, a majority of holes in a semiconductor layer 3 do not disappear by recombination with conduction electrons in the semiconductor layer 2, but reach the electrode layer 4 while diffusing into the semiconductor layer 2. Accordingly, the junction element 1 can serve as a good conductor for holes, while avoiding the influence of a resistance value, and allows a current to flow therethrough at a level equal to or more than that achieved by a semiconductor element formed of a Si or SiC semiconductor. The present invention is applicable to any semiconductor material in which at least one of a donor level and an acceptor level is located at a sufficiently deep position beyond a thermal excitation energy at an operating temperature, such as diamond, zinc oxide (ZnO), aluminum nitride (AlN), or boron nitride (BN). The present invention is also applicable to even a material having a shallow impurity level at room temperature, such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or germanium (Ge), as long as operation is performed at such a low temperature that the thermal excitation energy can be sufficiently small.

Abstract translation: 在该接合元件1中，当施加正向电压时，在半导体层2中形成耗尽层，禁止存在于电极层4中的电子移动到半导体层2中。因此，大部分孔 半导体层3不会通过与半导体层2中的导电电子的复合而消失，而是在扩散到半导体层2中的同时到达电极层4.因此，接合元件1可以用作孔的良导体，同时避免影响 的电阻值，并且允许电流以等于或大于由Si或SiC半导体形成的半导体元件实现的电平流过。 本发明可应用于任何半导体材料，其中施主电平和受主电平中的至少一个位于超过工作温度下的热激发能的足够深的位置，例如金刚石，氧化锌（ZnO），铝 氮化物（AlN）或氮化硼（BN）。 本发明甚至也可应用于诸如硅（Si），碳化硅（SiC），氮化镓（GaN），砷化镓（GaAs）或锗（Ge）等室温下具有浅杂质水平的材料， 只要在如此低的温度下进行操作即可使热激发能足够小。

公开(公告)号：US07611788B2

公开(公告)日：2009-11-03

申请号：US11595570

申请日：2006-11-09

Applicant: Hideaki Kikuchi ,  Masaaki Sakano ,  Yasuhiro Watanabe ,  Satoshi Tanimoto

Inventor： Hideaki Kikuchi ,  Masaaki Sakano ,  Yasuhiro Watanabe ,  Satoshi Tanimoto

IPC: H01M8/04 ,  H01M8/00 ,  H01M2/14

CPC classification number: H01M8/0267 ,  H01M8/0258 ,  H01M8/04029 ,  H01M8/04044 ,  H01M8/241 ,  H01M8/242 ,  H01M8/2483 ,  H01M2008/1095

Abstract: This fuel cell stack includes: a coolant-supplying penetration hole and a coolant-discharging penetration hole each communicating with a coolant passage and each penetrates unit fuel cells in a stacking direction. A coolant-supplying penetration hole and a coolant-discharging penetration hole are arranged in a horizontal direction opposing with each other so as to sandwich a power generating region. The fuel cell stack further includes: an air draining penetration hole communicating with the coolant passage and arranged such that at least one part thereof is located at a higher position than an uppermost position of the coolant passage, and penetrates the unit fuel cells in the stacking direction; and a coolant draining penetration hole communicating with the coolant passage and arranged such that at least one part thereof is located at a lower position than a lowermost position of the coolant passage, and penetrates the unit fuel cells in the stacking direction.

Abstract translation: 该燃料电池堆包括：冷却剂供给贯通孔和冷却剂排出贯通孔，其各自与冷却剂通路连通，并且各层在层叠方向上贯通单元燃料电池。 冷却剂供给贯通孔和冷却剂排出贯通孔在水平方向上彼此相对配置以夹住发电区域。 燃料电池堆还包括：与冷却剂通道连通的排气通孔，其布置成使得其至少一部分位于比冷却剂通道的最上位置更高的位置，并且在堆叠中穿透单元燃料电池 方向; 以及冷却剂排出贯通孔，其与冷却剂通路连通并且布置成使得其至少一部分位于比冷却剂通道的最低位置更低的位置处，并且沿堆叠方向穿透单元燃料电池。

公开(公告)号：US07535025B2

公开(公告)日：2009-05-19

申请号：US11003599

申请日：2004-12-06

Applicant: Satoshi Tanimoto ,  Hideyo Okushi

Inventor： Satoshi Tanimoto ,  Hideyo Okushi

IPC: H01L29/24

CPC classification number: H01L29/66068 ,  H01L29/1608 ,  H01L29/7395 ,  H01L29/7828 ,  H01L29/94

Abstract: In silicon carbide semiconductor device and manufacturing method therefor, a metal electrode which is another than a gate electrode and which is contacted with a singlecrystalline silicon carbide substrate is treated with a predetermined heat process at a temperature which is lower than a thermal oxidization temperature by which a gate insulating film is formed and is sufficient to carry out a contact annealing between the singlecrystalline silicon carbide substrate and a metal after a whole surrounding of the gate insulating film is enclosed with the singlecrystalline silicon carbide substrate, a field insulating film, and the gate electrode. The present invention is applicable to a MOS capacitor, an n channel planar power MOSFET, and an n channel planar power IGBT.

Abstract translation: 在碳化硅半导体器件及其制造方法中，以与栅极电极不同且与单晶碳化硅基板接触的金属电极在预定的热处理下，在低于热氧化温度的温度下进行处理， 形成栅极绝缘膜，并且足以在单晶碳化硅衬底和金属之间进行接触退火，整个栅极绝缘膜周围被单晶碳化硅衬底，场绝缘膜和栅极封闭 电极。 本发明可应用于MOS电容器，n沟道平面功率MOSFET和n沟道平面功率IGBT。