公开(公告)号：US20140191250A1

公开(公告)日：2014-07-10

申请号：US14234476

申请日：2012-07-27

申请人： Satoshi Tanimoto ,  Yusuke Zushi ,  Yoshinori Murakami ,  Takashi Iseki ,  Masato Takamori ,  Shinji Sato ,  Kohei Matsui

发明人： Satoshi Tanimoto ,  Yusuke Zushi ,  Yoshinori Murakami ,  Takashi Iseki ,  Masato Takamori ,  Shinji Sato ,  Kohei Matsui

IPC分类号： H01L23/00 ,  H01L29/16 ,  H01L29/20

CPC分类号： H01L29/1602 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/19 ,  B23K1/206 ,  B23K35/007 ,  B23K35/025 ,  B23K35/282 ,  B23K35/286 ,  B23K2101/34 ,  B23K2101/40 ,  B23K2101/42 ,  C22C18/04 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L29/1608 ,  H01L29/2003 ,  H01L2224/29118 ,  H01L2224/32225 ,  H01L2224/83001 ,  H01L2224/83203 ,  H01L2224/83447 ,  H01L2224/83815 ,  H01L2924/01322 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/01013 ,  H01L2924/0103 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device is carried out by readying each of a semiconductor element, a substrate having Cu as a principal element at least on a surface, and a ZnAl solder chip having a smaller shape than that of the semiconductor element; disposing the semiconductor element and the substrate so that respective bonding surfaces face each other, and sandwiching the ZnAl eutectic solder chip between the substrate and the semiconductor element; increasing the temperature of the ZnAl solder chip sandwiched between the substrate and the semiconductor element while applying a load to the ZnAl solder chip such that the ZnAl solder chip melts to form a ZnAl solder layer; and reducing the temperature of the ZnAl solder layer while applying a load to the ZnAl solder layer.

摘要翻译： 半导体器件的制造方法是通过将半导体元件，至少具有表面的Cu作为主要元素的基板和比半导体元件的形状小的ZnAl焊料芯片进行准位来进行的。 将所述半导体元件和所述基板配置为使得各个接合面彼此面对，并将所述ZnAl共晶焊料夹在所述基板和所述半导体元件之间; 在向ZnAl焊料芯片施加负载的同时，增加夹在基板和半导体元件之间的ZnAl焊料芯片的温度，使得ZnAl焊料芯片熔化形成ZnAl焊料层; 并且在向ZnAl焊料层施加负载的同时降低ZnAl焊料层的温度。

公开(公告)号：US08975182B2

公开(公告)日：2015-03-10

申请号：US14234476

申请日：2012-07-27

申请人： Satoshi Tanimoto ,  Yusuke Zushi ,  Yoshinori Murakami ,  Takashi Iseki ,  Masato Takamori ,  Shinji Sato ,  Kohei Matsui

发明人： Satoshi Tanimoto ,  Yusuke Zushi ,  Yoshinori Murakami ,  Takashi Iseki ,  Masato Takamori ,  Shinji Sato ,  Kohei Matsui

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  B23K35/28 ,  B23K35/00 ,  B23K35/02 ,  C22C18/04 ,  B23K1/00 ,  B23K1/008 ,  B23K1/19 ,  H01L29/16 ,  H01L29/20

CPC分类号： H01L29/1602 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/19 ,  B23K1/206 ,  B23K35/007 ,  B23K35/025 ,  B23K35/282 ,  B23K35/286 ,  B23K2101/34 ,  B23K2101/40 ,  B23K2101/42 ,  C22C18/04 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L29/1608 ,  H01L29/2003 ,  H01L2224/29118 ,  H01L2224/32225 ,  H01L2224/83001 ,  H01L2224/83203 ,  H01L2224/83447 ,  H01L2224/83815 ,  H01L2924/01322 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/01013 ,  H01L2924/0103 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device is carried out by readying each of a semiconductor element, a substrate having Cu as a principal element at least on a surface, and a ZnAl solder chip having a smaller shape than that of the semiconductor element; disposing the semiconductor element and the substrate so that respective bonding surfaces face each other, and sandwiching the ZnAl eutectic solder chip between the substrate and the semiconductor element; increasing the temperature of the ZnAl solder chip sandwiched between the substrate and the semiconductor element while applying a load to the ZnAl solder chip such that the ZnAl solder chip melts to form a ZnAl solder layer; and reducing the temperature of the ZnAl solder layer while applying a load to the ZnAl solder layer.

摘要翻译： 半导体器件的制造方法是通过将半导体元件，至少具有表面的Cu作为主要元素的基板和比半导体元件的形状小的ZnAl焊料芯片进行准位来进行的。 将所述半导体元件和所述基板配置为使得各个接合面彼此面对，并将所述ZnAl共晶焊料夹在所述基板和所述半导体元件之间; 在向ZnAl焊料芯片施加负载的同时，增加夹在基板和半导体元件之间的ZnAl焊料芯片的温度，使得ZnAl焊料芯片熔化形成ZnAl焊料层; 并且在向ZnAl焊料层施加负载的同时降低ZnAl焊料层的温度。

公开(公告)号：US08921998B2

公开(公告)日：2014-12-30

申请号：US14236236

申请日：2012-08-24

申请人： Yusuke Zushi ,  Yoshinori Murakami ,  Satoshi Tanimoto ,  Shinji Sato ,  Kohei Matsui

发明人： Yusuke Zushi ,  Yoshinori Murakami ,  Satoshi Tanimoto ,  Shinji Sato ,  Kohei Matsui

IPC分类号： H01L23/10 ,  H01L23/34 ,  H01L23/538 ,  H01L23/373 ,  H01L23/00 ,  H01L25/07 ,  H01L23/498 ,  H01L25/18

CPC分类号： H01L23/5384 ,  H01L23/3735 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48132 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor module has a pair of semiconductor devices, a heat sink, a first electrode, an output electrode and a second electrode. The semiconductor devices are connected in series with each other and have first terminals that are electrically connected to a first power system and a second terminal that is electrically connected to a second power system. The first electrode is electrically connected both to one of the first terminal and to an electrode of one of the semiconductor devices. The output electrode is electrically connected both to the second terminal and to an electrode of the other of the semiconductor device. The second electrode is electrically connected to the other of the first terminals. The second electrode is connected to the heat sink via a first insulating member. The output electrode is connected to the second electrode via a second insulating member.

摘要翻译： 半导体模块具有一对半导体器件，散热器，第一电极，输出电极和第二电极。 半导体器件彼此串联连接并且具有电连接到第一电力系统的第一端子和电连接到第二电力系统的第二端子。 第一电极电连接到第一端子中的一个和半导体器件中的一个的电极。 输出电极与第二端子和半导体器件的另一个的电极电连接。 第二电极与第一端子中的另一个电连接。 第二电极通过第一绝缘构件连接到散热器。 输出电极经由第二绝缘构件与第二电极连接。

公开(公告)号：US08916882B2

公开(公告)日：2014-12-23

申请号：US14116890

申请日：2012-05-11

申请人： Yusuke Zushi ,  Yoshinori Murakami ,  Satoshi Tanimoto ,  Shinji Sato ,  Kohei Matsui

发明人： Yusuke Zushi ,  Yoshinori Murakami ,  Satoshi Tanimoto ,  Shinji Sato ,  Kohei Matsui

IPC分类号： H03K17/16 ,  H01L27/06 ,  H02M1/08

CPC分类号： H01L27/0629 ,  H01L27/0682 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49111 ,  H01L2924/19105 ,  H02M1/08 ,  H03K17/04123 ,  H03K17/166 ,  H01L2924/00014

摘要： A switching circuit includes: a first switching element (Q1); a resistor (11) inserted between a control electrode (G) of the first switching element (Q1) and a control circuit (13) switching the first switching element (Q1); and a first capacitor (15) and a second switching element (14) connected in series between the control electrode (G) of the first switching element (Q1) and a low potential-side electrode (S) of the first switching element (Q1). A high potential-side electrode of the second switching element (14) is connected to the control electrode (G) of the first switching element (Q1). An electrode of the first capacitor (15) is connected to the low potential-side electrode (S) of the first switching element (Q1). A control electrode of the second switching element (14) is connected to an electrode of the resistor (11) connected to the control circuit (13).

摘要翻译： 开关电路包括：第一开关元件（Q1）; 插入在第一开关元件（Q1）的控制电极（G）和切换第一开关元件（Q1）的控制电路（13）之间的电阻器（11）; 以及串联连接在第一开关元件（Q1）的控制电极（G）和第一开关元件（Q1）的低电位侧电极（S）之间的第一电容器（15）和第二开关元件（14） ）。 第二开关元件（14）的高电位侧电极连接到第一开关元件（Q1）的控制电极（G）。 第一电容器（15）的电极与第一开关元件（Q1）的低电位侧电极（S）连接。 第二开关元件（14）的控制电极连接到与控制电路（13）连接的电阻器（11）的电极。

公开(公告)号：US20140159225A1

公开(公告)日：2014-06-12

申请号：US14236236

申请日：2012-08-24

申请人： Yusuke Zushi ,  Yoshinori Murakami ,  Satoshi Tanimoto ,  Shinji Sato ,  Kohei Matsui

发明人： Yusuke Zushi ,  Yoshinori Murakami ,  Satoshi Tanimoto ,  Shinji Sato ,  Kohei Matsui

IPC分类号： H01L23/538

CPC分类号： H01L23/5384 ,  H01L23/3735 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48132 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor module has a pair of semiconductor devices, a heat sink, a first electrode, an output electrode and a second electrode. The semiconductor devices are connected in series with each other and have first terminals that are electrically connected to a first power system and a second terminal that is electrically connected to a second power system. The first electrode is electrically connected both to one of the first terminal and to an electrode of one of the semiconductor devices. The output electrode is electrically connected both to the second terminal and to an electrode of the other of the semiconductor device. The second electrode is electrically connected to the other of the first terminals. The second electrode is connected to the heat sink via a first insulating member. The output electrode is connected to the second electrode via a second insulating member.

摘要翻译： 半导体模块具有一对半导体器件，散热器，第一电极，输出电极和第二电极。 半导体器件彼此串联连接并且具有电连接到第一电力系统的第一端子和电连接到第二电力系统的第二端子。 第一电极电连接到第一端子中的一个和半导体器件中的一个的电极。 输出电极与第二端子和半导体器件的另一个的电极电连接。 第二电极与第一端子中的另一个电连接。 第二电极通过第一绝缘构件连接到散热器。 输出电极经由第二绝缘构件与第二电极连接。

公开(公告)号：US20140091324A1

公开(公告)日：2014-04-03

申请号：US14116890

申请日：2012-05-11

申请人： Yusuke Zushi ,  Yoshinori Murakami ,  Satoshi Tanimoto ,  Shinji Sato ,  Kohei Matsui

发明人： Yusuke Zushi ,  Yoshinori Murakami ,  Satoshi Tanimoto ,  Shinji Sato ,  Kohei Matsui

IPC分类号： H01L27/06

CPC分类号： H01L27/0629 ,  H01L27/0682 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49111 ,  H01L2924/19105 ,  H02M1/08 ,  H03K17/04123 ,  H03K17/166 ,  H01L2924/00014

摘要： A switching circuit includes: a first switching element (Q1); a resistor (11) inserted between a control electrode (G) of the first switching element (Q1) and a control circuit (13) switching the first switching element (Q1); and a first capacitor (15) and a second switching element (14) connected in series between the control electrode (G) of the first switching element (Q1) and a low potential-side electrode (S) of the first switching element (Q1). A high potential-side electrode of the second switching element (14) is connected to the control electrode (G) of the first switching element (Q1). An electrode of the first capacitor (15) is connected to the low potential-side electrode (S) of the first switching element (Q1). A control electrode of the second switching element (14) is connected to an electrode of the resistor (11) connected to the control circuit (13).

摘要翻译： 开关电路包括：第一开关元件（Q1）; 插入在第一开关元件（Q1）的控制电极（G）和切换第一开关元件（Q1）的控制电路（13）之间的电阻器（11）; 以及串联连接在第一开关元件（Q1）的控制电极（G）和第一开关元件（Q1）的低电位侧电极（S）之间的第一电容器（15）和第二开关元件（14） ）。 第二开关元件（14）的高电位侧电极连接到第一开关元件（Q1）的控制电极（G）。 第一电容器（15）的电极与第一开关元件（Q1）的低电位侧电极（S）连接。 第二开关元件（14）的控制电极连接到与控制电路（13）连接的电阻器（11）的电极。

公开(公告)号：US20060022307A1

公开(公告)日：2006-02-02

申请号：US11189886

申请日：2005-07-27

申请人： Yoshinori Murakami

发明人： Yoshinori Murakami

IPC分类号： H01L27/108

CPC分类号： H01L23/051 ,  H01L23/3735 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2924/014

摘要： A semiconductor package has: a semiconductor chip having first and second main electrodes arranged on two principal surfaces being opposite to each other; a first main wiring plate connected to the first main electrode and having a first external connection terminal; a second main wiring plate connected to the second main electrode and having a second external connection terminal; a first shell connected through an insulating film to at least a part of a second principal surface of the first main wiring plate, the second principal surface of the first main wiring plate being opposite to a first principal surface of the first main wiring plate that is connected to the first electrode; and a second shell connected through an insulating film to at least a part of a second principal surface of the second main wiring plate, the second principal surface of the second main wiring plate being opposite to a first principal surface of the second main wiring plate that is connected to the second electrode. The first principal surfaces of the first and second main wiring plates are adjacent to and parallel to each other except at the locations where the first and second main wiring plates are connected to the semiconductor chip and the locations where the first and second external connection terminals are formed.

公开(公告)号：US20050259884A1

公开(公告)日：2005-11-24

申请号：US11130179

申请日：2005-05-17

申请人： Yoshinori Murakami ,  Hitoshi Hirohata

发明人： Yoshinori Murakami ,  Hitoshi Hirohata

IPC分类号： G06K9/36 ,  H04N1/405

CPC分类号： H04N1/4052

摘要： A quantization error calculation portion calculates the difference between the pixel value of a pixel of an input image added with an accumulative error by the adder and the quantization value obtained by quantizing the pixel value in the quantization processing portion as a quantization error. The quantization error is stored in the error storage portion. The multiplier multiplies, a quantization error to be distributed to a subsequently-quantized pixel, among the quantization errors stored in the error storage portion, by the diffusion coefficient numerator value corresponding to the quantization error. The adder adds the multiplication result produced by the multiplier. The divider divides the addition result produced by the adder by the diffusion coefficient denominator value. The division result is outputted to the adder as an accumulative error for a subsequently-quantized pixel.

摘要翻译： 量化误差计算部分计算由加法器添加的累积误差的输入图像的像素的像素值与通过量化量化处理部分中的像素值量化的量化值之间的差作为量化误差。 量化误差被存储在错误存储部分中。 通过与量化误差对应的扩散系数分子值，乘法器将存储在误差存储部分中的量化误差中的乘法器乘以要分配给后续量化像素的量化误差。 加法器加上由乘法器产生的相乘结果。 分频器将加法器产生的相加结果除以扩散系数分母值。 分割结果作为后续量化像素的累积误差输出到加法器。

公开(公告)号：US06930333B2

公开(公告)日：2005-08-16

申请号：US10883973

申请日：2004-07-06

申请人： Yoshinori Murakami

发明人： Yoshinori Murakami

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/495 ,  H01L23/498 ,  H01L29/417 ,  H01L29/74

CPC分类号： H01L23/49861 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L29/41716 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/16152 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device wiring structure is provided to reduce the wiring inductance and curtail the generation of interfering electromagnetic waves. A semiconductor chip having an anode electrode and a cathode electrode provided on two oppositely-facing main surfaces is sandwiched between a sheet-shaped anode wiring and a sheet-shaped cathode wiring. The anode and cathode electrodes of the semiconductor chip are connected to the anode and the cathode wirings, respectively, arranged such that the electric currents flowing there-through flow in opposite directions. A conductive substrate having a main surface with a larger width than the cathode wiring is disposed adjacent to the anode wiring. The edges of the cathode wiring protrude beyond the edges of both the anode wiring and the semiconductor chip in all locations and the dimension of the protrusion is at least one half of the distance from the edge of the cathode wiring to the metal substrate.

公开(公告)号：US20050121783A1

公开(公告)日：2005-06-09

申请号：US10998990

申请日：2004-11-30

申请人： Yoshinori Murakami

发明人： Yoshinori Murakami

IPC分类号： H01L23/34 ,  H01L23/367 ,  H01L23/538 ,  H02M7/04 ,  H02M7/48 ,  H01L23/495

CPC分类号： H01L23/5386 ,  F28D15/0233 ,  H01L23/367 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device mounting structure includes a bus bar of which a first end part is connected to a high-temperature power-purpose semiconductor device and a second end is connected to another device that is required to be kept at a lower temperature than the semiconductor device. The bus bar includes a ribbonlike part zigzagging between the first and second ends. The ribbonlike part of the bus bar can improve the cooling effect by increasing the length of the path through which the heat travels in the lengthwise direction of the bus bar. Thus, the heat emitted from the semiconductor device is prevented from being transferred to a peripheral circuit element through the bus bar used for supplying electric power to the circuit element from the semiconductor device.

摘要翻译： 半导体器件安装结构包括母线，第一端部连接到高温电力半导体器件，第二端连接到需要保持在比半导体器件低的温度的另一器件 。 母线包括在第一和第二端之间曲折的带状部分。 汇流条的带状部分可以通过增加热量在汇流条的长度方向上行进的路径的长度来改善冷却效果。 因此，防止从半导体器件发出的热量通过用于从半导体器件向电路元件供电的汇流条传送到外围电路元件。