公开(公告)号：US06974738B2

公开(公告)日：2005-12-13

申请号：US10834717

申请日：2004-04-28

申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta

发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/76 ,  H01L29/786 ,  H01L21/8238

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849

摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

公开(公告)号：US06787440B2

公开(公告)日：2004-09-07

申请号：US10315268

申请日：2002-12-10

申请人： Christopher G. Parker ,  Markus Kuhn ,  Ying Zhou ,  Scott A. Hareland ,  Suman Datta ,  Nick Lindert ,  Robert S. Chau ,  Timothy E. Glassman ,  Matthew V. Metz ,  Sunit Tyagi

发明人： Christopher G. Parker ,  Markus Kuhn ,  Ying Zhou ,  Scott A. Hareland ,  Suman Datta ,  Nick Lindert ,  Robert S. Chau ,  Timothy E. Glassman ,  Matthew V. Metz ,  Sunit Tyagi

IPC分类号： H01L214763

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

摘要： A method for making a semiconductor device is described. That method comprises forming on a substrate a buffer layer and a high-k gate dielectric layer, oxidizing the surface of the high-k gate dielectric layer, and then forming a gate electrode on the oxidized high-k gate dielectric layer.

公开(公告)号：US06887395B2

公开(公告)日：2005-05-03

申请号：US10364281

申请日：2003-02-10

申请人： Scott A. Hareland ,  Brian S. Doyle ,  Robert S. Chau

发明人： Scott A. Hareland ,  Brian S. Doyle ,  Robert S. Chau

IPC分类号： B44C1/22 ,  B81B1/00 ,  B81C1/00 ,  H01L21/00 ,  H01L29/06 ,  H01L29/12

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/0673 ,  Y10S438/947

摘要： A method is provided for forming sub-micron-size structures over a substrate. A width-defining step is formed over the substrate. A width-defining layer is formed over an edge of the width-defining step. The width-defining layer is etched back to leave a spacer adjacent the width-defining step. A length-defining step is formed over the substrate. A length-defining layer is formed over an edge of the length-defining step. The length-defining layer is etched back to leave a spacer adjacent a first edge of the length-defining step and across a first portion of the spacer left by the width-defining layer. The length-defining step is then removed. The spacer left by the width-defining layer is then etched with the spacer left by the length-defining layer serving as a mask, to form the structure.

摘要翻译： 提供了一种在衬底上形成亚微米级结构的方法。 在衬底上形成宽度限定步骤。 宽度限定层形成在宽度限定步骤的边缘上。 将宽度限定层回蚀刻以在宽度限定步骤附近留下间隔物。 在衬底上形成长度限定步骤。 长度限定层形成在长度限定步骤的边缘上。 长度限定层被回蚀刻以在与长度限定步骤的第一边缘相邻并且横跨由宽度限定层留下的间隔物的第一部分附近留下间隔物。 然后去除长度定义步骤。 然后由宽度限定层留下的间隔物用作为掩模的长度限定层留下的间隔物进行蚀刻，以形成结构。

公开(公告)号：US07078750B2

公开(公告)日：2006-07-18

申请号：US11026066

申请日：2004-12-30

申请人： Scott A. Hareland ,  Mark L. Doczy ,  Robert S. Chau

发明人： Scott A. Hareland ,  Mark L. Doczy ,  Robert S. Chau

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28185 ,  H01L21/26586 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： A method is described for selectively treating the properties of a gate dielectric near corners of the gate without altering the gate dielectric in a center region of a gate channel. The method includes providing a structure having a gate opening and depositing a layer of dielectric with a high dielectric constant on a bottom surface and side walls of the gate opening. The corner regions of the high dielectric constant layer formed adjacent to the bottom surface and the side walls of the gate opening are selectively treated without altering the center region of the high dielectric constant layer formed at the bottom surface of the gate opening.

摘要翻译： 描述了一种方法，用于选择性地处理在栅极角附近的栅极电介质的性质，而不改变栅极沟道的中心区域中的栅极电介质。 该方法包括提供具有栅极开口并且在栅极开口的底表面和侧壁上沉积具有高介电常数的电介质层的结构。 选择性地处理邻近底表面和栅极开口形成的高介电常数层的角区域，而不改变形成在栅极开口底表面处的高介电常数层的中心区域。

公开(公告)号：US07666727B2

公开(公告)日：2010-02-23

申请号：US11099190

申请日：2005-04-04

申请人： Brian Doyle ,  Scott A. Hareland ,  Mark Doczy ,  Robert S. Chau

发明人： Brian Doyle ,  Scott A. Hareland ,  Mark Doczy ,  Robert S. Chau

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/4983 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/32051 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659

摘要： A transistor comprising a gate electrode formed on a gate dielectric layer formed on a substrate. A pair of source/drain regions are formed in the substrate on opposite sides of the laterally opposite sidewalls of the gate electrode. The gate electrode has a central portion formed on the gate dielectric layer and over the substrate region between the source and drain regions and a pair sidewall portions which overlap a portion of the source/drain regions wherein the central portion has a first work function and said pair of sidewall portions has a second work function, wherein the second work function is different than the first work function.

摘要翻译： 一种晶体管，包括形成在形成于基板上的栅介质层上的栅电极。 在栅电极的横向相对的侧壁的相对侧上的衬底中形成一对源极/漏极区域。 栅极电极具有形成在栅极介电层上并且在源极和漏极区域之间的衬底区域上的中心部分和与源极/漏极区域的一部分重叠的一对侧壁部分，其中中心部分具有第一功函数和所述 一对侧壁部分具有第二功函数，其中第二功函数不同于第一功函数。

公开(公告)号：US07326652B2

公开(公告)日：2008-02-05

申请号：US11483295

申请日：2006-07-06

申请人： Robert S. Chau ,  Matthew V. Metz ,  Scott A. Hareland

发明人： Robert S. Chau ,  Matthew V. Metz ,  Scott A. Hareland

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/469

CPC分类号： C30B29/22 ,  C30B25/105 ,  C30B25/14 ,  C30B29/16

摘要： An atomic layer deposition process that reduces defective bonds formed when depositing atomic layers on a substrate or atomic layer when forming an integrated circuit device. As the layers are formed, a substrate or previous layer is exposed to a first reactant. After the substrate or layer has reacted with the first reactant, the substrate or layer is exposed to a second reactant. During or after exposure to the second reactant, electromagnetic radiation is applied to the substrate or layer. The electromagnetic radiation excites any defective bonds that may form in the deposition process to an energy level high enough to cause the elements forming the defective bonds to react with other elements contained in the second reactant. The reaction forms desirable bonds which attach to the substrate or previous layer to form an additional new layer.

摘要翻译： 当形成集成电路器件时，原子层沉积工艺可以减少在衬底或原子层上沉积原子层时形成的不良键。 当形成层时，将基底或先前的层暴露于第一反应物。 在衬底或层已经与第一反应物反应之后，衬底或层暴露于第二反应物。 在暴露于第二反应物期间或之后，电磁辐射被施加到基底或层上。 电磁辐射激发在沉积过程中可能形成的任何有缺陷的键，其能级高到足以导致形成缺陷键的元素与包含在第二反应物中的其它元素反应。 该反应形成了附着到基底或先前的层以形成另外的新层的理想的键。

公开(公告)号：US07101761B2

公开(公告)日：2006-09-05

申请号：US10746323

申请日：2003-12-23

申请人： Robert S. Chau ,  Scott A. Hareland ,  Justin K. Brask ,  Matthew V. Metz

发明人： Robert S. Chau ,  Scott A. Hareland ,  Justin K. Brask ,  Matthew V. Metz

IPC分类号： H01L21/336

CPC分类号： B82Y10/00 ,  G11C2213/17 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/785 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0512 ,  Y10S977/848

摘要： A method is described for providing a nanostructure suspended above a substrate surface. The method includes providing a nanostructure encased in an oxide shell on a substrate and depositing a sacrificial material and a support material over the oxide encased nanostructure. Then, the sacrificial material is removed to expose the oxide encased nanostructure. Once the oxide encased nanostructure has been exposed, the oxide shell is removed from the oxide encased nanostructure such that the nanostructure is suspended above the substrate surface.

摘要翻译： 描述了一种用于提供悬浮在衬底表面上方的纳米结构的方法。 该方法包括提供封装在衬底上的氧化物壳中的纳米结构，并在氧化物封装的纳米结构上沉积牺牲材料和载体材料。 然后，去除牺牲材料以暴露氧化物包裹的纳米结构。 一旦氧化物包裹的纳米结构已经暴露，氧化物壳被从氧化物封装的纳米结构中去除，使得纳米结构悬浮在衬底表面上方。

公开(公告)号：US07091129B2

公开(公告)日：2006-08-15

申请号：US10749347

申请日：2003-12-30

申请人： Robert S. Chau ,  Matthew V. Metz ,  Scott A. Hareland

发明人： Robert S. Chau ,  Matthew V. Metz ,  Scott A. Hareland

IPC分类号： H10L21/302 ,  H10L21/461 ,  H10L21/31 ,  H10L21/469

CPC分类号： C30B29/22 ,  C30B25/105 ,  C30B25/14 ,  C30B29/16

摘要： An atomic layer deposition process that reduces defective bonds formed when depositing atomic layers on a substrate or atomic layer when forming an integrated circuit device. As the layers are formed, a substrate or previous layer is exposed to a first reactant. After the substrate or layer has reacted with the first reactant, the substrate or layer is exposed to a second reactant. During or after exposure to the second reactant, electromagnetic radiation is applied to the substrate or layer. The electromagnetic radiation excites any defective bonds that may form in the deposition process to an energy level high enough to cause the elements forming the defective bonds to react with other elements contained in the second reactant. The reaction forms desirable bonds which attach to the substrate or previous layer to form an additional new layer.

公开(公告)号：US07078282B2

公开(公告)日：2006-07-18

申请号：US10749196

申请日：2003-12-30

申请人： Robert S. Chau ,  Justin K. Brask ,  Chris E. Barns ,  Scott A. Hareland

发明人： Robert S. Chau ,  Justin K. Brask ,  Chris E. Barns ,  Scott A. Hareland

IPC分类号： H01L21/338

CPC分类号： H01L29/66545 ,  H01L29/7842

摘要： The present invention relates to the deposition of a layer above a transistor structure, causing crystalline stress within the transistor, and resulting in increased performance. The stress layer may be formed above a plurality of transistors formed on a substrate, or above a plurality of selected transistors.

公开(公告)号：US07285829B2

公开(公告)日：2007-10-23

申请号：US10816232

申请日：2004-03-31

申请人： Brian Doyle ,  Scott A. Hareland ,  Mark Doczy ,  Robert S. Chau

发明人： Brian Doyle ,  Scott A. Hareland ,  Mark Doczy ,  Robert S. Chau

IPC分类号： H01L29/72

CPC分类号： H01L29/4983 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/32051 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659

摘要： A transistor comprising a gate electrode formed on a gate dielectric layer formed on a substrate. A pair of source/drain regions are formed in the substrate on opposite sides of the laterally opposite sidewalls of the gate electrode. The gate electrode has a central portion formed on the gate dielectric layer and over the substrate region between the source and drain regions and a pair sidewall portions which overlap a portion of the source/drain regions wherein the central portion has a first work function and said pair of sidewall portions has a second work function, wherein the second work function is different than the first work function.

摘要翻译： 一种晶体管，包括形成在形成于基板上的栅介质层上的栅电极。 在栅电极的横向相对的侧壁的相对侧上的衬底中形成一对源极/漏极区域。 栅极电极具有形成在栅极介电层上并且在源极和漏极区域之间的衬底区域上的中心部分和与源极/漏极区域的一部分重叠的一对侧壁部分，其中中心部分具有第一功函数和所述 一对侧壁部分具有第二功函数，其中第二功函数不同于第一功函数。