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    Method of fabricating a robust gate dielectric using a replacement gate flow
    2.
    发明授权
    Method of fabricating a robust gate dielectric using a replacement gate flow 失效
    使用更换栅流制造坚固的栅极电介质的方法

    公开(公告)号：US07078750B2

    公开(公告)日：2006-07-18

    申请号：US11026066

    申请日：2004-12-30

    申请人： Scott A. Hareland ,  Mark L. Doczy ,  Robert S. Chau

    发明人： Scott A. Hareland ,  Mark L. Doczy ,  Robert S. Chau

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/28185 ,  H01L21/26586 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

    摘要： A method is described for selectively treating the properties of a gate dielectric near corners of the gate without altering the gate dielectric in a center region of a gate channel. The method includes providing a structure having a gate opening and depositing a layer of dielectric with a high dielectric constant on a bottom surface and side walls of the gate opening. The corner regions of the high dielectric constant layer formed adjacent to the bottom surface and the side walls of the gate opening are selectively treated without altering the center region of the high dielectric constant layer formed at the bottom surface of the gate opening.

    摘要翻译： 描述了一种方法，用于选择性地处理在栅极角附近的栅极电介质的性质，而不改变栅极沟道的中心区域中的栅极电介质。 该方法包括提供具有栅极开口并且在栅极开口的底表面和侧壁上沉积具有高介电常数的电介质层的结构。 选择性地处理邻近底表面和栅极开口形成的高介电常数层的角区域，而不改变形成在栅极开口底表面处的高介电常数层的中心区域。

    Method of fabricating a robust gate dielectric using a replacement gate flow
    6.
    发明授权
    Method of fabricating a robust gate dielectric using a replacement gate flow 有权
    使用更换栅流制造坚固的栅极电介质的方法

    公开(公告)号：US06864145B2

    公开(公告)日：2005-03-08

    申请号：US10611109

    申请日：2003-06-30

    申请人： Scott A. Hareland ,  Mark L. Doczy ,  Robert S. Chau

    发明人： Scott A. Hareland ,  Mark L. Doczy ,  Robert S. Chau

    IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/51

    CPC分类号： H01L21/28185 ,  H01L21/26586 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

    摘要： A method is described for selectively treating the properties of a gate dielectric near corners of the gate without altering the gate dielectric in a center region of a gate channel. The method includes providing a structure having a gate opening and depositing a layer of dielectric with a high dielectric constant on a bottom surface and side walls of the gate opening. The corner regions of the high dielectric constant layer formed adjacent to the bottom surface and the side walls of the gate opening are selectively treated without altering the center region of the high dielectric constant layer formed at the bottom surface of the gate opening.

    摘要翻译： 描述了一种方法，用于选择性地处理在栅极角附近的栅极电介质的性质，而不改变栅极沟道的中心区域中的栅极电介质。 该方法包括提供具有栅极开口并且在栅极开口的底表面和侧壁上沉积具有高介电常数的电介质层的结构。 选择性地处理邻近底表面和栅极开口形成的高介电常数层的角区域，而不改变形成在栅极开口底表面处的高介电常数层的中心区域。

    Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
    10.
    发明授权
    Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication 有权
    非平面半导体器件部分或完全缠绕在栅极电极和制造方法

    公开(公告)号：US07456476B2

    公开(公告)日：2008-11-25

    申请号：US10607769

    申请日：2003-06-27

    申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    IPC分类号： H01L29/786

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795

    摘要： A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

    摘要翻译： 描述了非平面半导体器件及其制造方法。 非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。 在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。 栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。 在栅电极的相对侧的半导体本体中形成一对源/漏区。