公开(公告)号：US4748487A

公开(公告)日：1988-05-31

申请号：US053479

申请日：1987-05-26

申请人： Hideaki Uchida ,  Kinya Mitsumoto ,  Yoshiaki Yazawa ,  Shinji Nakazato ,  Masanori Odaka

发明人： Hideaki Uchida ,  Kinya Mitsumoto ,  Yoshiaki Yazawa ,  Shinji Nakazato ,  Masanori Odaka

IPC分类号： H01L21/8238 ,  G11C11/34 ,  G11C11/419 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H01L27/02

CPC分类号： G11C11/419 ,  H01L27/11

摘要： A semiconductor memory device wherein the equivalent series resistances that are interposed in series in the pairs of complementary data lines D, D, are substantially the same as one another among the individual complementary data lines D, D. The equivalent series resistance is comprised of pull-up MISFET's and column switching MISFET's that exist between the power source V.sub.CC and the sense circuit. Parity is maintained for the pull-up MISFET's (Q.sub.p, Q.sub.p) and the column switching MISFET's (Q.sub.y, Q.sub.y) that exist on the pairs of complementary data lines D, D. To maintain this parity, the two MISFET's are formed to have the same shape. In addition, the arrangement of contacts to the transistors are set so that the directions in which the currents flow and lengths of current paths are also the same. In other words, contact portions between aluminum electrode and source and drain regions are formed at the same positions in the two MISFET's.

摘要翻译： 一种半导体存储器件，其中在互补数据线对D，＆amp; D和D中的串联插入的等效串联电阻在各个互补数据线D，＆amp; L和D之间彼此基本相同。等效串联电阻包括 上拉MISFET和列切换MISFET存在于电源VCC和感测电路之间。 维持上拉MISFET（Qp，Qp）和在互补数据线D和上拉和下降D上存在的列切换MISFET（Qy，Qy）的奇偶校验。为了保持这个奇偶校验，两个MISFET的形成是 相同的形状。 此外，设置与晶体管的接触的布置，使得电流流动的方向和电流路径的长度也相同。 换句话说，铝电极和源极和漏极区域之间的接触部分形成在两个MISFET的相同位置处。

公开(公告)号：US20070188208A1

公开(公告)日：2007-08-16

申请号：US11783382

申请日：2007-04-09

申请人： Kinya Mitsumoto

发明人： Kinya Mitsumoto

IPC分类号： H03K3/356

CPC分类号： H03K3/356113 ,  H03K3/012 ,  H03K2217/0018

摘要： In a semiconductor integrated circuit including first and second circuits whose inputs/outputs are in cross-connection, an output node of the first circuit is driven on the basis of a first input signal, and an output node of the second circuit is driven on the basis of a second input signal. At this time, there are provided a first driving transistor capable of driving the output node of the first circuit on the basis of the second input signal, and a second driving transistor capable of driving the output node of the second circuit on the basis of the first input signal. The output nodes are driven using the first and second driving transistors, respectively.

摘要翻译： 在包括输入/​​输出交叉连接的第一和第二电路的半导体集成电路中，基于第一输入信号驱动第一电路的输出节点，并且第二电路的输出节点被驱动 第二输入信号的基础。 此时，提供了能够基于第二输入信号驱动第一电路的输出节点的第一驱动晶体管，以及能够基于第二驱动晶体管驱动第二电路的输出节点的第二驱动晶体管 第一输入信号。 输出节点分别使用第一和第二驱动晶体管驱动。

公开(公告)号：US20060145266A1

公开(公告)日：2006-07-06

申请号：US11322377

申请日：2006-01-03

申请人： Hirofumi Zushi ,  Kinya Mitsumoto

发明人： Hirofumi Zushi ,  Kinya Mitsumoto

IPC分类号： H01L29/94 ,  H01L29/76

CPC分类号： H01L27/1203 ,  H01L27/0207 ,  H01L29/41733 ,  H01L29/7846 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor integrated circuit, whose MOS transistors' layout structure is determined in consideration of the size of a device active region in a gate length direction, in which each transistor is formed. When stresses coming from the device isolation region, etc. are taken into account, for a circuit whose current driving power reduction caused by the stresses should be suppressed, the distance between the device isolation regions in the gate length direction may be selected so as to suppress the reduction in drain-source current. Further, for a circuit whose logical threshold voltage variations caused by the stresses should be suppressed, the distance between the device isolation regions in the gate length direction may be selected so that the variations in drain-source current caused by such stresses are balanced between the p-channel and n-channel transistors. Characteristic variations arising in the transistors owing to stresses coming from the device isolation region, etc. are selectively used, whereby a desired performance required for the circuit is achieved readily.

摘要翻译： 考虑到形成每个晶体管的栅极长度方向上的器件有源区的大小来确定MOS晶体管的布局结构的半导体集成电路。 当考虑到来自器件隔离区域等的应力时，对于应该抑制由应力引起的电流驱动功率降低的电路，可以选择栅极长度方向上的器件隔离区域之间的距离，以便 抑制漏源电流的降低。 此外，对于应该抑制由应力引起的逻辑阈值电压变化的电路，可以选择器件隔离区域在栅极长度方向上的距离，使得由这种应力引起的漏极 - 源极电流的变化在 p沟道和n沟道晶体管。 选择性地使用由于来自器件隔离区域的应力引起的晶体管中产生的特征变化等，从而容易地实现电路所需的性能。

公开(公告)号：US06909312B2

公开(公告)日：2005-06-21

申请号：US10766945

申请日：2004-01-30

申请人： Kinya Mitsumoto

发明人： Kinya Mitsumoto

IPC分类号： G06F1/06 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/13 ,  H03L7/00 ,  H03L7/06 ,  H03L7/081 ,  H03L7/087 ,  H03L7/089 ,  H03L7/095 ,  H03L7/099 ,  H03L7/107 ,  H03L7/16 ,  H03L7/191 ,  H04L7/04

CPC分类号： H03L7/0805 ,  H03L7/0812 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/0995 ,  H03L7/191

摘要： Phase synchronization is achieved by forming a first pulse to be synchronized with a reference pulse, a second pulse leading in phase for a certain period relative to said first pulse and a third pulse delayed in phase for a certain period from said first pulse; comparing said reference pulse with said first pulse in a first comparing; comparing said reference pulse with said second pulse and said third pulse in a second comparing; and forming a control voltage by giving priority to a comparison output of said second comparing with respect to a comparison output of said first comparing, matching the phase of said reference pulse with the phrase of said second pulse or said third pulse, and matching, after said matching of phases, the phrase of said reference pulse with the phase of said first pulse by forming said control, voltage from the comparison output of said first comparing.

摘要翻译： 通过形成与参考脉冲同步的第一脉冲，相对于所述第一脉冲相位导通一定时间的第二脉冲和从所述第一脉冲一段时间相位延迟的第三脉冲来实现相位同步; 在第一比较中比较所述参考脉冲与所述第一脉冲; 在第二比较中比较所述参考脉冲与所述第二脉冲和所述第三脉冲; 并且通过将所述第二比较的比较输出优先于所述第一比较的比较输出，将所述参考脉冲的相位与所述第二脉冲或所述第三脉冲的短语进行匹配，并且在 所述相位匹配，通过形成所述控制的所述第一脉冲的相位的所述参考脉冲的短语，来自所述第一比较的比较输出的电压。

公开(公告)号：US20050104642A1

公开(公告)日：2005-05-19

申请号：US10983722

申请日：2004-11-09

申请人： Kinya Mitsumoto

发明人： Kinya Mitsumoto

IPC分类号： H03K3/012 ,  H03K3/356 ,  H03K3/037

CPC分类号： H03K3/356113 ,  H03K3/012 ,  H03K2217/0018

摘要： In a semiconductor integrated circuit including first and second circuits whose inputs/outputs are in cross-connection, an output node of the first circuit is driven on the basis of a first input signal, and an output node of the second circuit is driven on the basis of a second input signal. At this time, there are provided a first driving transistor capable of driving the output node of the first circuit on the basis of the second input signal, and a second driving transistor capable of driving the output node of the second circuit on the basis of the first input signal. The output nodes are driven using the first and second driving transistors, respectively.

摘要翻译： 在包括输入/​​输出交叉连接的第一和第二电路的半导体集成电路中，基于第一输入信号驱动第一电路的输出节点，并且第二电路的输出节点被驱动 第二输入信号的基础。 此时，提供了能够基于第二输入信号驱动第一电路的输出节点的第一驱动晶体管，以及能够基于第二驱动晶体管驱动第二电路的输出节点的第二驱动晶体管 第一输入信号。 输出节点分别使用第一和第二驱动晶体管驱动。

公开(公告)号：US5734616A

公开(公告)日：1998-03-31

申请号：US694059

申请日：1996-08-08

申请人： Hideto Kazama ,  Shuichi Miyaoka ,  Akihiko Emori ,  Kinya Mitsumoto ,  Tomoyuki Someya ,  Masahiro Iwamura ,  Noboru Akiyama

发明人： Hideto Kazama ,  Shuichi Miyaoka ,  Akihiko Emori ,  Kinya Mitsumoto ,  Tomoyuki Someya ,  Masahiro Iwamura ,  Noboru Akiyama

IPC分类号： G11C11/419 ,  G11C7/00

CPC分类号： G11C11/419

摘要： A static RAM includes pre-amplifiers, which are made up solely of emitter-follower transistors having their collectors supplied with the power voltage, in one-to-one correspondence to sub common data line pairs which are connected by column switches to complementary data line pairs of memory arrays. The pre-amplifier is provided with a first switch which turns on during the selected state to connect the sub common data line pair to the bases of the transistors and a second switch which turns on during the unselected state to provide the bases with a certain bias voltage lower than the readout signal voltage on the sub common data line pair. The emitter-follower transistors have their emitters connected commonly to form common emitter lines, which are connected to pairs of input terminals of main amplifiers made up of CMOS transistors.

摘要翻译： 静态RAM包括前置放大器，其仅由具有其电源电压的集电极的射极跟随器晶体管组成，与通过列开关连接到互补数据线的子公共数据线对一一对应 成对的存储器阵列。 前置放大器设置有在选择状态期间导通的第一开关，以将子公共数据线对连接到晶体管的基极;以及第二开关，其在未选择状态期间导通，以向基极提供一定的偏置 电压低于副公共数据线对上的读出信号电压。 射极跟随器晶体管的发射极共同连接形成共同的发射极线，其连接到由CMOS晶体管构成的主放大器的输入端对。

公开(公告)号：US4665505A

公开(公告)日：1987-05-12

申请号：US685552

申请日：1984-12-24

申请人： Nobuaki Miyakawa ,  Yoshiaki Yazawa ,  Shoichi Ozeki ,  Kinya Mitsumoto

发明人： Nobuaki Miyakawa ,  Yoshiaki Yazawa ,  Shoichi Ozeki ,  Kinya Mitsumoto

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C11/40

CPC分类号： G11C7/1096 ,  G11C7/1078

摘要： A write circuit for a semiconductor storage device which comprises a data output stage constructed by a composite circuit including at least one MOS transistor logic circuit and bipolar transistor. The Mos transistor circuit operates in response to an input signal to control the on-off states of at least one of the bipolar transistors. The write circuit implements less power consumption.

摘要翻译： 一种用于半导体存储装置的写入电路，包括由包括至少一个MOS晶体管逻辑电路和双极晶体管的复合电路构成的数据输出级。 Mos晶体管电路响应于输入信号而工作，以控制至少一个双极晶体管的导通截止状态。 写入电路实现更少的功耗。

公开(公告)号：US07196424B2

公开(公告)日：2007-03-27

申请号：US10982920

申请日：2004-11-08

申请人： Noriyuki Itano ,  Kinya Mitsumoto

发明人： Noriyuki Itano ,  Kinya Mitsumoto

IPC分类号： H01L23/48

CPC分类号： H03L7/0812 ,  G06F1/04 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20

摘要： A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor chip, mounting terminals, and a first signal path for receiving a signal output from the predetermined one of the pad electrodes and transmitting the signal to other one of the pad electrodes. The first signal path includes delay elements comparable to delays in a second signal path extending from the predetermined one of the mounting terminals to the other one of the mounting terminals through the semiconductor chip, and is disposed on a feedback path for phase comparison for synchronizing the phase of an output signal from the second signal path to the phase of an input signal to the second signal path.

摘要翻译： 一种具有与其中的半导体芯片连接的封装电路部分的半导体器件。 半导体芯片包括多个焊盘电极，封装电路部分包括连接到半导体芯片上的焊盘电极的布线，安装端子，以及用于接收从预定的一个焊盘电极输出的信号的第一信号路径， 信号到另一个焊盘电极。 第一信号路径包括延迟元件，该延迟元件与从安装端子中的预定安装端子到另一个安装端子延伸穿过半导体芯片的第二信号路径中的延迟相比较，并且设置在用于相位比较的反馈路径上用于使 从第二信号路径到输入信号到第二信号路径的相位的输出信号的相位。

公开(公告)号：US20060284296A1

公开(公告)日：2006-12-21

申请号：US11514101

申请日：2006-09-01

申请人： Noriyuki Itano ,  Kinya Mitsumoto

发明人： Noriyuki Itano ,  Kinya Mitsumoto

IPC分类号： H01L23/02

CPC分类号： H03L7/0812 ,  G06F1/04 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20

摘要： A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor chip, mounting terminals, and a first signal path for receiving a signal output from the predetermined one of the pad electrodes and transmitting the signal to other one of the pad electrodes. The first signal path includes delay elements comparable to delays in a second signal path extending from the predetermined one of the mounting terminals to the other one of the mounting terminals through the semiconductor chip, and is disposed on a feedback path for phase comparison for synchronizing the phase of an output signal from the second signal path to the phase of an input signal to the second signal path.

公开(公告)号：US20050232386A1

公开(公告)日：2005-10-20

申请号：US11156473

申请日：2005-06-21

申请人： Kinya Mitsumoto

发明人： Kinya Mitsumoto

IPC分类号： G06F1/06 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/13 ,  H03L7/00 ,  H03L7/06 ,  H03L7/081 ,  H03L7/087 ,  H03L7/089 ,  H03L7/095 ,  H03L7/099 ,  H03L7/107 ,  H03L7/16 ,  H03L7/191 ,  H04L7/04

CPC分类号： H03L7/0805 ,  H03L7/0812 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/0995 ,  H03L7/191

摘要： In a synchronization circuit and a synchronization method, a first variable delay circuit generates a first pulse to be synchronized with a reference pulse, a second pulse which is leading in the phase to the first pulse, and a third pulse which is delayed in the phase from the first pulse. The reference pulse and the first pulse are compared by a first phase comparing circuit, and the reference pulse, second pulse and third pulse are compared by a second phase comparing circuit. A control voltage generating circuit forms a control voltage by giving priority to a comparison output of the second phase comparing circuit against a comparison output of the first phase comparing circuit. Delay time of the first variable delay circuit is controlled after the phases are matched by forming the control voltage with the comparison output of the first phase comparing circuit.

摘要翻译： 在同步电路和同步方法中，第一可变延迟电路产生与参考脉冲同步的第一脉冲，在第一脉冲的相位中引出的第二脉冲和相位延迟的第三脉冲 从第一脉冲。 参考脉冲和第一脉冲通过第一相位比较电路进行比较，并且通过第二相位比较电路比较参考脉冲，第二脉冲和第三脉冲。 控制电压产生电路通过优先考虑第二相位比较电路的比较输出与第一相位比较电路的比较输出而形成控制电压。 通过用第一相位比较电路的比较输出形成控制电压，在相位匹配之后，控制第一可变延迟电路的延迟时间。