公开(公告)号：US09905696B2

公开(公告)日：2018-02-27

申请号：US15450391

申请日：2017-03-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichi Koezuka ,  Toshinari Sasaki ,  Katsuaki Tochibayashi ,  Shunpei Yamazaki

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L27/12 ,  H01L27/32 ,  H01L27/146 ,  G02F1/1368 ,  H01L27/15 ,  G02F1/1362

CPC classification number: H01L29/78606 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/1339 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2201/121 ,  G06F3/0412 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/14612 ,  H01L27/14616 ,  H01L27/15 ,  H01L27/3258 ,  H01L27/3262 ,  H01L29/66742 ,  H01L29/7869

Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.

公开(公告)号：US09780219B2

公开(公告)日：2017-10-03

申请号：US15351775

申请日：2016-11-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichi Koezuka ,  Toshinari Sasaki ,  Katsuaki Tochibayashi ,  Shunpei Yamazaki

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L27/146 ,  G02F1/133 ,  G02F1/1333 ,  G02F1/1339 ,  G02F1/1343 ,  G02F1/1368 ,  G06F3/041 ,  H01L27/32

CPC classification number: H01L29/78606 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/1339 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2201/121 ,  G06F3/0412 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/14612 ,  H01L27/14616 ,  H01L27/15 ,  H01L27/3258 ,  H01L27/3262 ,  H01L29/66742 ,  H01L29/7869

Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.

公开(公告)号：US09773919B2

公开(公告)日：2017-09-26

申请号：US15235242

申请日：2016-08-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya Sasagawa ,  Takashi Hamada ,  Akihisa Shimomura ,  Satoru Okamoto ,  Katsuaki Tochibayashi

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/4757 ,  H01L21/4763 ,  H01L21/465 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L21/465 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42372 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78648

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor.

公开(公告)号：US09553202B2

公开(公告)日：2017-01-24

申请号：US14489074

申请日：2014-09-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Motomu Kurata ,  Shinya Sasagawa ,  Ryota Hodo ,  Katsuaki Tochibayashi ,  Tomoaki Moriwaka ,  Jiro Nishida ,  Hidekazu Miyairi ,  Shunpei Yamazaki

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L27/1207 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/5226 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/13 ,  H01L29/66969 ,  H01L29/7869

Abstract: The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.

Abstract translation: 半导体器件包括第一层，第一层包括第一晶体管，第二层，包括第一层上的第一绝缘膜，第三层，包括第二层上的第二绝缘膜;以及第四层，包括第三层上的第二晶体管 。 第一导电膜通过设置在第一绝缘膜中的开口将第一晶体管和第二晶体管彼此电连接。 第二导电膜通过设置在第二绝缘膜中的开口将第一晶体管，第二晶体管和第一导电膜彼此电连接。 第一晶体管的沟道形成区域包括单晶半导体。 第二晶体管的沟道形成区域包括氧化物半导体。 第二导电膜的底面的宽度为5nm以下。

公开(公告)号：US09293589B2

公开(公告)日：2016-03-22

申请号：US13746751

申请日：2013-01-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Junichi Koezuka ,  Kenichi Okazaki ,  Terumasa Ikeyama ,  Katsuaki Tochibayashi

IPC: H01L21/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/7869 ,  H01L21/385 ,  H01L29/045 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606

Abstract: A highly reliable semiconductor device including a transistor using an oxide semiconductor is provided. In a semiconductor device including a bottom-gate transistor including an oxide semiconductor layer, a first insulating layer is formed in contact with the oxide semiconductor layer, and an oxygen doping treatment is performed thereon, whereby the first insulating layer is made to contain oxygen in excess of the stoichiometric composition. The formation of the second insulating layer over the first insulating layer enables excess oxygen included in the first insulating layer to be supplied efficiently to the oxide semiconductor layer. Accordingly, the highly reliable semiconductor device with stable electric characteristics can be provided.

Abstract translation: 提供了包括使用氧化物半导体的晶体管的高度可靠的半导体器件。 在包括具有氧化物半导体层的底栅晶体管的半导体器件中，形成与氧化物半导体层接触的第一绝缘层，并在其上进行氧掺杂处理，由此使第一绝缘层含有氧 过量的化学计量组成。 在第一绝缘层上形成第二绝缘层使得能够有效地向氧化物半导体层提供包括在第一绝缘层中的过量的氧。 因此，可以提供具有稳定电特性的高度可靠的半导体器件。

公开(公告)号：US09147773B2

公开(公告)日：2015-09-29

申请号：US14336127

申请日：2014-07-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Katsuaki Tochibayashi ,  Satoshi Higano ,  Shunpei Yamazaki

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/465 ,  H01L29/66

CPC classification number: H01L29/78693 ,  H01L21/02071 ,  H01L21/32136 ,  H01L21/465 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

Abstract: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device is manufactured with a high yield to achieve high productivity. In the manufacture of a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are sequentially stacked and a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film, the source electrode layer and the drain electrode layer are formed through an etching step and then a step for removing impurities which are generated by the etching step and exist on a surface of the oxide semiconductor film and in the vicinity thereof is performed.

Abstract translation: 提供了一种高度可靠的半导体器件和半导体器件的制造方法。 以高产率制造半导体器件以实现高生产率。 在制造其中栅极电极层，栅极绝缘膜和氧化物半导体膜依次层叠的晶体管和提供与氧化物半导体膜接触的源电极层和漏电极层的晶体管的半导体器件的制造中， 通过蚀刻步骤形成源电极层和漏电极层，然后进行用于除去由蚀刻步骤产生并存在于氧化物半导体膜的表面及其附近的杂质的步骤。

公开(公告)号：US09040396B2

公开(公告)日：2015-05-26

申请号：US14169837

申请日：2014-01-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masami Jintyou ,  Yamato Aihara ,  Katsuaki Tochibayashi ,  Toru Arakawa

IPC: H01L21/20 ,  H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/0237 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/441 ,  H01L21/47573 ,  H01L29/045 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78606 ,  H01L29/7869

Abstract: An object is to provide a technique by which a semiconductor device including a high-performance and high-reliable transistor is manufactured. A protective conductive film which protects an oxide semiconductor layer when a wiring layer is formed from a conductive layer is formed between the oxide semiconductor layer and the conductive layer, and an etching process having two steps is performed. In a first etching step, an etching is performed under conditions that the protective conductive film is less etched than the conductive layer and the etching selectivity of the conductive layer to the protective conductive film is high. In a second etching step, etching is performed under conditions that the protective conductive film is more easily etched than the oxide semiconductor layer and the etching selectivity of the protective conductive film to the oxide semiconductor layer is high.

Abstract translation: 本发明的目的是提供一种制造包括高性能和高可靠性晶体管的半导体器件的技术。 在氧化物半导体层和导电层之间形成由导电层形成布线层时保护氧化物半导体层的保护导电膜，并且进行具有两个步骤的蚀刻工艺。 在第一蚀刻步骤中，在保护导电膜比导电层蚀刻少的条件下进行蚀刻，并且导电层对保护导电膜的蚀刻选择性高。 在第二蚀刻步骤中，在保护导电膜比氧化物半导体层更容易蚀刻的条件下进行蚀刻，并且保护性导电膜对氧化物半导体层的蚀刻选择性高。

公开(公告)号：US20140287552A1

公开(公告)日：2014-09-25

申请号：US14219111

申请日：2014-03-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Taiga Muraoka ,  Motomu Kurata ,  Shinya Sasagawa ,  Katsuaki Tochibayashi

IPC: H01L21/70 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/02554 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02565 ,  H01L21/02667 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/32139 ,  H01L29/66969 ,  H01L29/7869

Abstract: A stable and minute processing method of a thin film is provided. Further, a miniaturized semiconductor device is provided. A method for processing a thin film includes the following steps: forming a film to be processed over a formation surface; forming an organic coating film over the film to be processed; forming a resist film over the organic coating film; exposing the resist film to light_or_an electron beam; removing part of the resist film by development to expose part of the organic coating film; depositing an organic material layer on the top surface and a side surface of the resist film by plasma treatment; etching part of the organic coating film using the resist film and the organic material layer as masks to expose part of the film to be processed; and etching part of the film to be processed using the resist film and the organic material layer as masks.

Abstract translation: 提供了薄膜的稳定和微小的加工方法。 此外，提供了一种小型化的半导体器件。 一种处理薄膜的方法包括以下步骤：在地层表面上形成待处理的薄膜; 在待处理的膜上形成有机涂膜; 在有机涂膜上形成抗蚀膜; 将抗蚀剂膜暴露于light_or_an电子束; 通过显影去除部分抗蚀剂膜以暴露部分有机涂膜; 通过等离子体处理在抗蚀剂膜的顶表面和侧表面上沉积有机材料层; 使用所述抗蚀剂膜和所述有机材料层作为掩模蚀刻所述有机涂膜的一部分，以暴露待处理膜的部分; 并使用抗蚀剂膜和有机材料层作为掩模蚀刻待处理的膜的一部分。

公开(公告)号：US08815640B2

公开(公告)日：2014-08-26

申请号：US13652668

申请日：2012-10-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Katsuaki Tochibayashi ,  Satoshi Higano ,  Shunpei Yamazaki

IPC: H01L29/26 ,  H01L21/46

CPC classification number: H01L29/66969 ,  H01L29/22 ,  H01L29/7869

Abstract: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. In a semiconductor device including a bottom-gate transistor in which an insulating layer functioning as a channel protective film is provided over an oxide semiconductor film, elements contained in an etching gas can be prevented from remaining as impurities on a surface of the oxide semiconductor film by performing impurity-removing process after formation of an insulating layer provided over and in contact with the oxide semiconductor film and/or formation of source and drain electrode layers. The impurity concentration in the surface of the oxide semiconductor film is lower than or equal to 5×1018 atoms/cm3, preferably lower than or equal to 1×1018 atoms/cm3.

Abstract translation: 提供了一种高度可靠的半导体器件和半导体器件的制造方法。 在包含作为沟道保护膜的绝缘层设置在氧化物半导体膜上的底栅晶体管的半导体器件中，可以防止包含在蚀刻气体中的元素作为杂质残留在氧化物半导体膜的表面上 通过在形成设置在氧化物半导体膜上并与氧化物半导体膜接触并且/或形成源极和漏极电极层的绝缘层之后进行杂质去除处理。 氧化物半导体膜表面的杂质浓度低于或等于5×1018原子/ cm3，优选为1×1018原子/ cm3以下。

公开(公告)号：US12100768B2

公开(公告)日：2024-09-24

申请号：US17606823

申请日：2020-05-12

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Ryota Hodo ,  Katsuaki Tochibayashi ,  Hiroaki Honda ,  Kentaro Sugaya

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78651

Abstract: A semiconductor device with small variations in transistor characteristics is provided. The semiconductor device includes an oxide; a first conductor and a second conductor provided apart from each other over the oxide; an insulator in a region between the first conductor and the second conductor over the oxide; and a conductor over the insulator. A side surface of the oxide, a top surface of the first conductor, a side surface of the first conductor, a top surface of the second conductor, and a side surface of the second conductor include regions in contact with a nitride containing silicon.