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43 条记录 (耗时 0.04 秒)

    Method for forming a vertical transistor having tensile layers
    21.
    发明授权
    Method for forming a vertical transistor having tensile layers 有权
    用于形成具有拉伸层的垂直晶体管的方法

    公开(公告)号：US08093127B2

    公开(公告)日：2012-01-10

    申请号：US12329190

    申请日：2008-12-05

    申请人： Eun Sung Lee

    发明人： Eun Sung Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7827 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66666

    摘要： A vertical transistor includes a semiconductor substrate provided with a pillar type active pattern over the surface thereof. A first tensile layer is formed over the semiconductor substrate and around the lower end portion of the pillar type active pattern, and a second tensile layer is formed over the upper end portion of the pillar type active pattern so that a tensile stress is applied in a vertical direction to the pillar type active pattern. A first junction region is formed within the surface of the semiconductor substrate below the first tensile layer and the pillar type active pattern. A gate is formed so as to surround at least a portion of the pillar type active pattern. A second junction region is formed within the upper end portion of the pillar type active pattern.

    摘要翻译： 垂直晶体管包括在其表面上设置有柱状有源图案的半导体衬底。 第一拉伸层形成在半导体基板上并且在柱状有源图案的下端部周围，并且第二拉伸层形成在柱状活性图案的上端部分上，使得拉伸应力在 与柱式活动图案垂直的方向。 第一接合区形成在第一拉伸层和柱状活性图案下方的半导体基板的表面内。 形成栅极以包围柱状有源图案的至少一部分。 第二接合区形成在柱状有源图案的上端部内。

    Vertical transistor having first and second tensile layers
    25.
    发明授权
    Vertical transistor having first and second tensile layers 失效
    具有第一和第二拉伸层的垂直晶体管

    公开(公告)号：US08569832B2

    公开(公告)日：2013-10-29

    申请号：US13314532

    申请日：2011-12-08

    申请人： Eun Sung Lee

    发明人： Eun Sung Lee

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/7827 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66666

    摘要： A vertical transistor includes a semiconductor substrate provided with a pillar type active pattern over the surface thereof. A first tensile layer is formed over the semiconductor substrate and around the lower end portion of the pillar type active pattern, and a second tensile layer is formed over the upper end portion of the pillar type active pattern so that a tensile stress is applied in a vertical direction to the pillar type active pattern. A first junction region is formed within the surface of the semiconductor substrate below the first tensile layer and the pillar type active pattern. A gate is formed so as to surround at least a portion of the pillar type active pattern. A second junction region is formed within the upper end portion of the pillar type active pattern.

    摘要翻译： 垂直晶体管包括在其表面上设置有柱状有源图案的半导体衬底。 第一拉伸层形成在半导体基板上并且在柱状有源图案的下端部周围，并且第二拉伸层形成在柱状活性图案的上端部分上，使得拉伸应力在 与柱式活动图案垂直的方向。 第一接合区形成在第一拉伸层和柱状活性图案下方的半导体基板的表面内。 形成栅极以包围柱状有源图案的至少一部分。 第二接合区形成在柱状有源图案的上端部内。

    Conductive Paste, And Electronic Device And Solar Cell Including An Electrode Formed Using The Same
    26.
    发明申请
    Conductive Paste, And Electronic Device And Solar Cell Including An Electrode Formed Using The Same 有权
    导电膏，电子器件和太阳能电池，包括使用其形成的电极

    公开(公告)号：US20120180859A1

    公开(公告)日：2012-07-19

    申请号：US13307932

    申请日：2011-11-30

    申请人： Eun Sung Lee ,  Se Yun Kim ,  Sang Soo Jee ,  Yong Nam Ham

    发明人： Eun Sung Lee ,  Se Yun Kim ,  Sang Soo Jee ,  Yong Nam Ham

    IPC分类号： H01L31/0224 ,  H01B1/02

    CPC分类号： H01L31/022425 ,  H01B1/22 ,  Y02E10/50

    摘要： A conductive paste includes a conductive powder, a metallic glass, and an organic vehicle. The metallic glass includes a first element, a second element having a higher absolute value of Gibbs free energy of oxide formation than the first element, and a third element having an absolute value of Gibbs free energy of oxide formation of about 1000 kJ/mol or less at a baking temperature and a eutectic temperature with the conductive powder of less than about 1000° C. An electronic device and a solar cell may include an electrode formed using the conductive paste.

    摘要翻译： 导电浆料包括导电粉末，金属玻璃和有机载体。 金属玻璃包括第一元件，具有比第一元素更高的氧化物形成吉布斯自由能绝对值的第二元素，以及具有大约1000kJ / mol的氧化物形成的吉布斯自由能的绝对值的第三元素，或 导电粉末的烘烤温度和共晶温度小于约1000℃。电子器件和太阳能电池可以包括使用导电浆料形成的电极。

    Zero capacitor RAM with reliable drain voltage application and method for manufacturing the same
    28.
    发明授权
    Zero capacitor RAM with reliable drain voltage application and method for manufacturing the same 失效
    零电容RAM具有可靠的漏极电压应用及其制造方法

    公开(公告)号：US08148243B2

    公开(公告)日：2012-04-03

    申请号：US12972998

    申请日：2010-12-20

    申请人： Eun Sung Lee

    发明人： Eun Sung Lee

    IPC分类号： H01L21/36

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802

    摘要： The following discloses and describes a zero capacitor RAM as well as a method for manufacturing the same. The zero capacitor RAM includes an SOI substrate. This SOI substrate is composed of a stacked structure of a silicon substrate, an embedded insulation film and a silicon layer. This layer is patterned into line types to constitute active patterns. Moreover, a first insulation layer forms between the active patterns and gates form on the active patterns as well as the first insulation layer to extend perpendicularly to the active patterns. In addition, a source forms in the active pattern on one side of each gate, a drain forms in the active pattern on the other side of each gate which is achieved by filling a metal layer. Continuing, a contact plug forms between the gates on the source and an interlayer dielectric forms on the contact plug in addition to the gates Finally, a bit line forms on the interlayer dielectric to extend perpendicularly to the gates and come into contact with the drain.

    摘要翻译： 以下公开并描述了零电容器RAM及其制造方法。 零电容RAM包括SOI衬底。 该SOI衬底由硅衬底，嵌入绝缘膜和硅层的堆叠结构组成。 该层被图案化成行类型以构成活动模式。 此外，在活性图案之间形成有源图案和栅极之间形成的第一绝缘层以及垂直于有源图案延伸的第一绝缘层。 此外，源极在每个栅极的一侧形成有源图案，在每个栅极的另一侧的有源图案中形成漏极，这是通过填充金属层而实现的。 继续地，在栅极之间形成接触插塞，除了栅极之外，在接触插塞上形成层间电介质。最后，在层间电介质上形成位线，以垂直于栅极延伸并与漏极接触。