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218 条记录 (耗时 0.03 秒)

    Air gap for interconnect application
    23.
    发明授权
    Air gap for interconnect application 有权
    互连应用的气隙

    公开(公告)号：US07682963B2

    公开(公告)日：2010-03-23

    申请号：US11867308

    申请日：2007-10-04

    申请人： Hai-Ching Chen ,  Sunil Kumar Singh ,  Tien-I Bao ,  Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Hai-Ching Chen ,  Sunil Kumar Singh ,  Tien-I Bao ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a method for fabricating an integrated circuit. The method includes forming an energy removable film (ERF) on a substrate; forming a first dielectric layer on the ERF; patterning the ERF and first dielectric layer to form a trench in the ERF and the first dielectric layer; filling a conductive material in the trench; forming a ceiling layer on the first dielectric layer and conductive material filled in the trench; and applying energy to the ERF to form air gaps in the ERF after the forming of the ceiling layer.

    摘要翻译： 本公开提供了一种用于制造集成电路的方法。 该方法包括在基板上形成能量可去除膜（ERF）; 在ERF上形成第一介电层; 图案化ERF和第一介电层以在ERF和第一介电层中形成沟槽; 在沟槽中填充导电材料; 在第一介电层上形成顶层和填充在沟槽中的导电材料; 并且在形成天花板层之后，向ERF施加能量以在ERF中形成气隙。

    AIR GAP FOR INTERCONNECT APPLICATION
    24.
    发明申请
    AIR GAP FOR INTERCONNECT APPLICATION 有权
    用于互连应用的空气隙

    公开(公告)号：US20090091038A1

    公开(公告)日：2009-04-09

    申请号：US11867308

    申请日：2007-10-04

    申请人： Hai-Ching Chen ,  Sunil Kumar Singh ,  Tien-I Bao ,  Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Hai-Ching Chen ,  Sunil Kumar Singh ,  Tien-I Bao ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a method for fabricating an integrated circuit. The method includes forming an energy removable film (ERF) on a substrate; forming a first dielectric layer on the ERF; patterning the ERF and first dielectric layer to form a trench in the ERF and the first dielectric layer; filling a conductive material in the trench; forming a ceiling layer on the first dielectric layer and conductive material filled in the trench; and applying energy to the ERF to form air gaps in the ERF after the forming of the ceiling layer.

    摘要翻译： 本公开提供了一种用于制造集成电路的方法。 该方法包括在基板上形成能量可去除膜（ERF）; 在ERF上形成第一介电层; 图案化ERF和第一介电层以在ERF和第一介电层中形成沟槽; 在沟槽中填充导电材料; 在第一介电层上形成顶层和填充在沟槽中的导电材料; 并且在形成天花板层之后，向ERF施加能量以在ERF中形成气隙。

    Sidewall coverage for copper damascene filling
    25.
    发明授权
    Sidewall coverage for copper damascene filling 有权
    铜镶嵌填料的侧壁覆盖

    公开(公告)号：US07282450B2

    公开(公告)日：2007-10-16

    申请号：US10733722

    申请日：2003-12-11

    申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

    摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

    摘要翻译： 描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。 具体应用是用铜填充沟槽以形成镶嵌线。 首先，通过PVD将种子层沉积在孔或沟槽中。 然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。 描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

    Method of passivating a metal line prior to deposition of a fluorinated silica glass layer
    27.
    发明授权
    Method of passivating a metal line prior to deposition of a fluorinated silica glass layer 有权
    在沉积氟化石英玻璃层之前钝化金属线的方法

    公开(公告)号：US06242338B1

    公开(公告)日：2001-06-05

    申请号：US09422175

    申请日：1999-10-22

    申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Yao-yi Cheng ,  Chen-Hua Yu ,  Mei-Yun Wang

    发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Yao-yi Cheng ,  Chen-Hua Yu ,  Mei-Yun Wang

    IPC分类号： H01L214763

    CPC分类号： H01L21/02131 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31629 ,  H01L21/321 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76888

    摘要： A process of forming a thin, protective insulator layer, on the sides of metal interconnect structures, prior to the deposition of a halogen containing, low k dielectric layer, has been developed. The process features the growth of a thin metal nitride, or thin metal oxide layer, on the exposed sides of the metal interconnect structures, via a plasma treatment, performed in either a nitrogen containing, or in a water containing, ambient. The thin layer protects the metal interconnect structure from the corrosive, as well as delamination effects, created by the halogen, or halogen products, contained in overlying low k dielectric layers, such as fluorinated silica glass.

    摘要翻译： 已经开发了在沉积含卤素的低k电介质层之前在金属互连结构的侧面上形成薄的保护性绝缘体层的工艺。 该方法的特征在于金属互连结构的暴露侧上通过等离子体处理在含氮或含水环境中进行的金属氮化物或薄金属氧化物层的生长。 薄层保护金属互连结构免受由覆盖在低k电介质层（例如氟化石英玻璃）中的卤素或卤素产物产生的腐蚀性以及分层影响。

    Self-passivation of copper damascene
    28.
    发明授权
    Self-passivation of copper damascene 失效
    铜大马士革自钝化

    公开(公告)号：US6083835A

    公开(公告)日：2000-07-04

    申请号：US121707

    申请日：1998-07-24

    申请人： Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L21/768 ,  H01L21/44

    CPC分类号： H01L21/76856 ,  H01L21/7684 ,  H01L21/76849

    摘要： A process for forming damascene wiring within an integrated circuit is described. After the trenches have been filled and planarized, normal dishing of the copper is present. This is then eliminated by depositing a layer of a chrome-copper alloy over the damascene wiring and then planarizing this layer so that it covers only the copper in the damascene trench. Then, while the IMD is deposited, some of the chromium in the alloy gets selectively oxidized, resulting in a self-aligned barrier layer of chromium oxide at the copper to IMD interface.

    摘要翻译： 描述了在集成电路内形成镶嵌线的工艺。 在沟槽被填充和平坦化之后，存在铜的正常凹陷。 然后通过在大马士革布线上沉积一层铬铜合金，然后平坦化该层，使其仅覆盖大马士革沟槽中的铜而消除。 然后，当沉积IMD时，合金中的一些铬被选择性地氧化，导致在铜到IMD界面处的氧化铬的自对准势垒层。

    Copper interconnect structure and method for forming the same
    29.
    发明授权
    Copper interconnect structure and method for forming the same 有权
    铜互连结构及其形成方法

    公开(公告)号：US08941239B2

    公开(公告)日：2015-01-27

    申请号：US13586676

    申请日：2012-08-15

    申请人： Chen-Hua Yu ,  Shau-Lin Shue ,  Hsiang-Huan Lee ,  Ching-Fu Yeh

    发明人： Chen-Hua Yu ,  Shau-Lin Shue ,  Hsiang-Huan Lee ,  Ching-Fu Yeh

    IPC分类号： H01L23/48 ,  H01L21/14

    CPC分类号： H01L21/76871 ,  H01L21/76846 ,  H01L2221/1089

    摘要： A copper interconnect structure in a semiconductor device including an opening formed in a dielectric layer of the semiconductor device, the opening having sidewalls and a bottom. A first barrier layer is conformally deposited on the sidewalls and the bottom of the opening. A first seed layer is conformally deposited on the first barrier layer. A second barrier layer is conformally deposited on the first seed layer. A second seed layer is conformally deposited on the second barrier layer and a conductive plug is deposited in the opening of the dielectric layer.

    摘要翻译： 一种半导体器件中的铜互连结构，包括形成在半导体器件的电介质层中的开口，该开口具有侧壁和底部。 第一阻挡层保形地沉积在开口的侧壁和底部上。 第一种子层共形沉积在第一阻挡层上。 第二阻挡层被共形沉积在第一籽晶层上。 第二种子层被共形沉积在第二阻挡层上，并且导电塞被沉积在电介质层的开口中。