公开(公告)号：US20120129318A1

公开(公告)日：2012-05-24

申请号：US13298522

申请日：2011-11-17

申请人： Hideto OHNUMA ,  Hideomi SUZAWA

发明人： Hideto OHNUMA ,  Hideomi SUZAWA

IPC分类号： H01L21/762 ,  C23F1/08

CPC分类号： H01J37/32825 ,  H01J37/32935 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76254 ,  H01L22/12 ,  H01L22/26

摘要： The atmospheric pressure plasma etching apparatus is provided with a state detecting unit for detecting a state of the object to be processed, and the operation of the atmospheric pressure plasma etching apparatus is controlled in accordance with information detected by the state detecting unit. Thus, in the atmospheric pressure plasma etching apparatus, the object to be processed can be etched while the state of the object to be processed is detected. Accordingly, the object to be processed can be etched favorably. Further, an SOI substrate is manufactured using the atmospheric pressure plasma etching apparatus, whereby both reduction in manufacturing cost of the SOI substrate and suppression of peeling in the SOI substrate can be achieved.

摘要翻译： 大气压等离子体蚀刻装置设置有用于检测待处理物体的状态的状态检测单元，并且根据由状态检测单元检测到的信息来控制大气压等离子体蚀刻装置的操作。 因此，在大气压等离子体蚀刻装置中，可以在检测待处理物体的状态的同时蚀刻被处理物。 因此，可以有利地蚀刻待加工的物体。 此外，使用大气压等离子体蚀刻装置制造SOI衬底，由此可以实现SOI衬底的制造成本的降低和SOI衬底中的剥离的抑制。

公开(公告)号：US20110250723A1

公开(公告)日：2011-10-13

申请号：US13078020

申请日：2011-04-01

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA

IPC分类号： H01L21/336

CPC分类号： H01L29/78636 ,  G11C16/0433 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/7869

摘要： In an embodiment, an insulating film is formed over a flat surface; a mask is formed over the insulating film; a slimming process is performed on the mask; an etching process is performed on the insulating film using the mask; a conductive film covering the insulating film is formed; a polishing process is performed on the conductive film and the insulating film, so that the conductive film and the insulating film have equal thicknesses; the conductive film is etched, so that a source electrode and a drain electrode which are thinner than the conductive film are formed; an oxide semiconductor film is formed in contact with the insulating film, the source electrode, and the drain electrode; a gate insulating film covering the oxide semiconductor film is formed; and a gate electrode is formed in a region which is over the gate insulating film and overlaps with the insulating film.

摘要翻译： 在一个实施例中，在平坦表面上形成绝缘膜; 在绝缘膜上形成掩模; 在面罩上进行减肥过程; 使用掩模对绝缘膜进行蚀刻处理; 形成覆盖绝缘膜的导电膜; 对导电膜和绝缘膜进行抛光处理，使得导电膜和绝缘膜具有相等的厚度; 蚀刻导电膜，形成比导电膜薄的源电极和漏电极; 形成与绝缘膜，源电极和漏电极接触的氧化物半导体膜; 形成覆盖氧化物半导体膜的栅极绝缘膜; 并且栅电极形成在栅极绝缘膜上并与绝缘膜重叠的区域中。

公开(公告)号：US20090134462A1

公开(公告)日：2009-05-28

申请号：US12361923

申请日：2009-01-29

申请人： Hideomi SUZAWA ,  Yasuhiko TAKEMURA

发明人： Hideomi SUZAWA ,  Yasuhiko TAKEMURA

IPC分类号： H01L27/12

CPC分类号： H01L29/78636 ,  H01L27/12 ,  H01L27/1244 ,  H01L27/1248 ,  Y10S257/90

摘要： A semiconductor integrated circuit comprising thin-film transistors in each of which the second wiring is prevented from breaking at steps. A silicon nitride film is formed on gate electrodes and on gate wiring extending from the gate electrodes. Substantially triangular regions are formed out of an insulator over side surfaces of the gate electrodes and of the gate wiring. The presence of these substantially triangular side walls make milder the steps at which the second wiring goes over the gate wiring. This suppresses breakage of the second wiring.

摘要翻译： 一种包括薄膜晶体管的半导体集成电路，其中每个薄膜晶体管中的第二布线都被防止在步骤中断开。 在栅电极和从栅电极延伸的栅极布线上形成氮化硅膜。 在栅极电极和栅极布线的侧表面上形成由绝缘体构成的基本上三角形的区域。 这些基本上三角形的侧壁的存在使得第二布线越过栅极布线的步骤变得更加温和。 这抑制了第二布线的破损。

公开(公告)号：US20120061670A1

公开(公告)日：2012-03-15

申请号：US13220736

申请日：2011-08-30

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1262 ,  H01L21/44 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

摘要： Described is a method for manufacturing a semiconductor device. A mask is formed over an insulating film and the mask is reduced in size. An insulating film having a projection is formed using the mask reduced in size, and a transistor whose channel length is reduced is formed using the insulating film having a projection. Further, in manufacturing the transistor, a planarization process is performed on a surface of a gate insulating film which overlaps with a top surface of a fine projection. Thus, the transistor can operate at high speed and the reliability can be improved. In addition, the insulating film is processed into a shape having a projection, whereby a source electrode and a drain electrode can be formed in a self-aligned manner.

摘要翻译： 描述了一种用于制造半导体器件的方法。 在绝缘膜上形成掩模，并且掩模的尺寸减小。 使用尺寸减小的掩模形成具有突起的绝缘膜，并且使用具有突起的绝缘膜形成沟道长度减小的晶体管。 此外，在制造晶体管时，在与微细突起的顶面重叠的栅极绝缘膜的表面上进行平坦化处理。 因此，晶体管可以高速运转，可提高可靠性。 此外，绝缘膜被加工成具有突起的形状，由此可以以自对准的方式形成源电极和漏电极。

公开(公告)号：US20110117698A1

公开(公告)日：2011-05-19

申请号：US13012987

申请日：2011-01-25

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC分类号： H01L21/465

CPC分类号： H01L27/127 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/167 ,  G09F21/04 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

摘要： An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

摘要翻译： 本发明的目的是建立一种其中使用氧化物半导体的半导体器件的制造中的加工技术。 在基板上形成栅电极，在栅电极上形成栅极绝缘层，在栅极绝缘层上形成氧化物半导体层，通过湿蚀刻加工氧化物半导体层，形成岛状氧化物半导体层 形成导电层以覆盖岛状氧化物半导体层，通过干蚀刻处理导电层以形成源电极，并且通过干蚀刻除去漏电极和岛状氧化物半导体层的一部分， 在岛状氧化物半导体层中形成凹部。

公开(公告)号：US20100105162A1

公开(公告)日：2010-04-29

申请号：US12582074

申请日：2009-10-20

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC分类号： H01L21/336 ,  H01L21/34

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L29/7869

摘要： In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. The etching step is performed by dry etching in which an etching gas is used.

摘要翻译： 在制造包括通道蚀刻反交错薄膜晶体管的半导体器件的方法中，使用使用作为曝光的多色调掩模形成的掩模层来蚀刻氧化物半导体膜和导电膜 光透过该掩模以具有多个强度。 蚀刻步骤通过使用蚀刻气体的干蚀刻进行。

公开(公告)号：US20100099216A1

公开(公告)日：2010-04-22

申请号：US12580512

申请日：2009-10-16

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC分类号： H01L21/336

CPC分类号： H01L27/127 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/167 ,  G09F21/04 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

摘要： An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

摘要翻译： 本发明的目的是建立一种其中使用氧化物半导体的半导体器件的制造中的加工技术。 在基板上形成栅电极，在栅电极上形成栅极绝缘层，在栅极绝缘层上形成氧化物半导体层，通过湿蚀刻加工氧化物半导体层，形成岛状氧化物半导体层 形成导电层以覆盖岛状氧化物半导体层，通过干蚀刻处理导电层以形成源电极，并且通过干蚀刻除去漏电极和岛状氧化物半导体层的一部分， 在岛状氧化物半导体层中形成凹部。

公开(公告)号：US20100068860A1

公开(公告)日：2010-03-18

申请号：US12621537

申请日：2009-11-19

申请人： Hongyong ZHANG ,  Yasuhiko TAKEMURA ,  Toshimitsu KONUMA ,  Hideto OHNUMA ,  Naoaki YAMAGUCHI ,  Hideomi SUZAWA ,  Hideki UOCHI

发明人： Hongyong ZHANG ,  Yasuhiko TAKEMURA ,  Toshimitsu KONUMA ,  Hideto OHNUMA ,  Naoaki YAMAGUCHI ,  Hideomi SUZAWA ,  Hideki UOCHI

IPC分类号： H01L21/336

CPC分类号： H01L27/127 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.

摘要翻译： 提供了一种方法，通过该方法可以容易地形成轻掺杂漏极（LDD）区域，并且在具有覆盖有氧化物覆盖层的栅电极的薄膜晶体管中的源/漏区域中以良好的产率形成。 通过以栅极电极作为掩模，以自对准的方式将杂质引入岛状硅膜中形成轻掺杂漏极（LDD）区域。 首先，通过使用旋转 - 倾斜离子注入在岛状硅膜中形成低浓度杂质区，以相对于衬底从倾斜方向进行离子掺杂。 此时也在栅电极下方形成低浓度杂质区。 之后，将高浓度的杂质通常引入衬底，从而形成高浓度杂质区域。 在上述过程中，低浓度杂质区域保留在栅电极下方并构成轻掺杂漏区。

公开(公告)号：US20090239354A1

公开(公告)日：2009-09-24

申请号：US12399047

申请日：2009-03-06

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light.

摘要翻译： 在单晶半导体基板的表面上形成绝缘膜，在单晶半导体基板中通过用离子束照射单晶半导体基板通过绝缘膜形成脆性区域，在绝缘膜上形成接合层， 通过将支撑基板和单晶半导体基板之间的接合层插入到单晶半导体基板的支撑基板上，将单晶半导体基板分割为脆性区域，将单晶半导体基板分离成单晶半导体层， 所述支撑基板对残留在所述单晶半导体层上的所述脆性区域的一部分进行第一干蚀刻处理，对经过所述第一蚀刻处理的所述单晶半导体层的表面进行第二干蚀刻处理， 具有激光的晶体半导体层。

公开(公告)号：US20120286267A1

公开(公告)日：2012-11-15

申请号：US13557719

申请日：2012-07-25

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC分类号： H01L33/08

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L29/7869

摘要： In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. The etching step is performed by dry etching in which an etching gas is used.

摘要翻译： 在制造包括通道蚀刻反交错薄膜晶体管的半导体器件的方法中，使用使用作为曝光的多色调掩模形成的掩模层来蚀刻氧化物半导体膜和导电膜 光透过该掩模以具有多个强度。 蚀刻步骤通过使用蚀刻气体的干蚀刻进行。